參數(shù)資料
型號(hào): SAA2502
廠商: NXP Semiconductors N.V.
英文描述: ISO/MPEG Audio Source Decoder
中文描述: 的ISO / MPEG音頻信源解碼器
文件頁(yè)數(shù): 45/64頁(yè)
文件大小: 318K
代理商: SAA2502
1997 Nov 17
45
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
Table 55
Preferred allocations
DOM1
DOM0
FUNCTION
REMARKS
0
0
1
1
0
1
0
1
data from microcontroller to SAA2500
data from SAA2500 to microcontroller
control from microcontroller to SAA2500
status from SAA2500 to microcontroller
general purpose data transfer
general purpose data transfer
register selection for data transfer
short device status message
handbook, halfpage
0
1
2
3
4
5
6
7
L3CLK
L3DATA
MGB505
Fig.21 Addressing mode.
The meaning of the bits on L3DATA.
Bit 0 and bit 1; these are the Data Operation Mode (DOM) bits that indicate the nature of the following data transfer. The preferred allocations are
given in Table 55.
Bit 2 to bit 7; these bits act as 6 bit operational IC address, with bit 7 as MSB and bit 2 as LSB.
8.1.1.2
Data mode
In the data mode the microcontroller sends or receives
information to or from the selected device. During data
transfer the L3MODE line is HIGH. The L3CLK line is
lowered 8 times during which the L3DATA line carries
8 bits. The information is presented LSB first and remains
stable during the LOW phase of the L3CLK signal.
The basic data transfer unit is an 8-bit byte. No other basic
data transfer unit is allowed.
8.1.1.3
Halt mode
In between transfer units the L3MODE line will be driven
LOW by the microcontroller to indicate the completion of a
unit transfer. This is called ‘Halt Mode’ (HM). During halt
mode the L3CLK line remains HIGH (to distinguish it from
an addressing mode).
handbook, halfpage
0
1
2
3
4
5
6
7
L3CLK
L3DATA
MGB504
Fig.22 Data transfer mode.
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