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參數(shù)資料
| 型號： | SAA2502 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ISO/MPEG Audio Source Decoder |
| 中文描述： | 的ISO / MPEG音頻信源解碼器 |
| 文件頁數(shù)： | 25/64頁 |
| 文件大?。?/td> | 318K |
| 代理商： | SAA2502 |
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1997 Nov 17
25
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
Table 15
Channel status data
Notes
1.
This field is filled according to clause 4.2.2.2 of the SPDIF standard ‘Channel status data format for digital audio
equipment for consumer use’ (mode 0).
The low sample frequencies of MPEG2 are not defined yet. In order to be able to follow future standardization, the
code sent for the three remaining sampling frequencies (24, 22.05 and 16 kHz) is programmable through the
controller interface.
The remaining 162 bits of each channel status word will all be logic 0. Individual bits of the status channel will be sent
bit 0 first.
2.
3.
DESCRIPTION
BITS
FIELD
INDICATION
Control field; note 1
0
1
0
0
indicates consumer use
logic 1 reserved for digital data and further
standardization
logic 0 = copy prohibited; logic 1 = copy permitted
no pre-emphasis (SAA2502 has automatic
de-emphasis)
2 channel audio data
mode 0 indication
2 channel
don’t care
don’t care
field filled in accordance with clause 4.2.2.2 of the SPDIF standard:
0100 = 48 kHz
0000 = 44.1 kHz
1100 = 32 kHz
field filled in accordance with clause 4.2.2.2 of the SPDIF standard:
00= level II (normal accuracy of 0.1%)
2
3 and 4
C
00
5
6 and 7
8 to 15
16 to 19
20 to 23
24 to 27
0
00
00000000
0000
0000
Category code
Source number
Channel number
Sample frequency;
note 2
Clock accuracy; note 3
28 and 29
7.5.2.6
Parity (bit 31, SPDIF sub-frame, P bit)
Even parity is generated on the 28 sub-frame data bits
(4 to 31) in bit 31.
7.5.2.7
SPDIF control
The SPDIF interface will be controlled by the
microcontroller via the control interface. The V bit is copied
into each SPDIF subframe (once for each data sample).
The C bit is inserted twice per SPDIF super-frame into the
channel status data (bit 2 in each C channel). The user
byte is inserted into the user channel (preceded by a start
bit) immediately after reception through the control
interface, otherwise the user channel is filled with logic 0s.
Table 16
SPDIF interface control
7.5.2.8
Channel status
The sampling frequency bits (bits 24 to 27) are derived
from the sampling frequency index bits of the input data
stream
7.5.2.9
User data
Only single 8 bit messages are sent. Individual messages
should be time separated far enough to insert at least
9 logic 0s in between (for easy synchronization at the
receiver end at random entry points in the stream).
BIT/BYTE
DEFAULT
RESULT
V bit
C bit
U byte
default = logic 0
default = logic 1
uuuuuuuu
valid audio data
digital copy permitted
8 bits user byte
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA2502H | ISO/MPEG Audio Source Decoder |
| SAA2503 | MPEG2 audio decoder(MPEG2 音頻譯碼器) |
| SAA2503HT | MPEG2 audio decoder |
| SAA2505H-M1 | Digital multi-channel audio IC DUET |
| SAA2505 | Digital multi-channel audio IC DUET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA2502H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ISO/MPEG Audio Source Decoder |
| SAA2503 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder |
| SAA2503HT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder |
| SAA2505 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET |
| SAA2505H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET |
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