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您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄25635 > S80C32XXX-16R (ATMEL CORP) 8-BIT, 16 MHz, MICROCONTROLLER, PQCC44 PDF資料下載

型號(hào)：	S80C32XXX-16R
廠商：	ATMEL CORP
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, 16 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	947/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S80C32XXX-16R

32072H–AVR32–10/2012

AT32UC3A3

When a breakpoint triggers, the CPU enters OCD mode, and instructions are fetched from the

Debug Instruction OCD register. Each time this register is written by JTAG, the instruction is

executed, allowing the JTAG to execute CPU instructions directly. The JTAG master can e.g.

read out the register file by issuing mtdr instructions to the CPU, writing each register to the

Debug Communication Channel OCD registers.

monitor mode

Since the OCD registers are directly accessible by the CPU, it is possible to build a software-

based debugger that runs on the CPU itself. Setting the Monitor Mode bit in the Development

Control register causes the CPU to enter monitor mode instead of OCD mode when a breakpoint

triggers. Monitor mode is similar to OCD mode, except that instructions are fetched from the

debug exception vector in regular program memory, instead of issued by JTAG.

program counter monitoring

Normally, the CPU would need to be halted for a JTAG-based debugger to examine the current

PC value. However, the AT32UC3A3 provides a Debug Program Counter OCD register, where

the debugger can continuously read the current PC without affecting the CPU. This allows the

debugger to generate a simple statistic of the time spent in various areas of the code, easing

code optimization.

Memory Service Unit

The Memory Service Unit (MSU) is a block dedicated to test and debug functionality. It is con-

trolled through a dedicated set of registers addressed through the MEMORY_SERVICE JTAG

Cyclic Redundancy Check (CRC)

The MSU can be used to automatically calculate the CRC of a block of data in memory. The

OCD will then read out each word in the specified memory block and report the CRC32-value in

an OCD register.

The MSU additionally supports NanoTrace. This is an AVR32-specific feature, in which trace

data is output to memory instead of the AUX port. This allows the trace data to be extracted by

JTAG MEMORY_ACCESS, enabling trace features for JTAG-based debuggers. The user must

write MSU registers to configure the address and size of the memory block to be used for Nano-

Trace. The NanoTrace buffer can be anywhere in the physical address range, including internal

and external RAM, through an EBI, if present. This area may not be used by the application run-

ning on the CPU.

AUX-based Debug Features

Utilizing the Auxiliary (AUX) port gives access to a wide range of advanced debug features. Of

prime importance are the trace features, which allow an external debugger to receive continuous

information on the program execution in the CPU. Additionally, Event In and Event Out pins

allow external events to be correlated with the program flow.

The AUX port contains a number of pins, as shown in Table 35-5 on page 932. These are multi-

plexed with I/O Controller lines, and must explicitly be enabled by writing OCD registers before

the debug session starts. The AUX port is mapped to two different locations, selectable by OCD

Registers, minimizing the chance that the AUX port will need to be shared with an application.

相關(guān)PDF資料	PDF描述
S80C52CXXX-16	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
S80C52CXXX-25SHXXX	8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:D	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:R	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-40SHXXX:RD	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C376CB8 WAF	制造商:Intel 功能描述:
S80C42	制造商:Intel 功能描述:
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S80C51-12	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S80C51-16	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller

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