514
32072H–AVR32–10/2012
AT32UC3A3
Figure 24-7. Receiver Clock Management
24.7.1.4
Serial clock ratio considerations
The transmitter and the receiver can be programmed to operate with the clock signals provided
on either the TX_CLOCK or RX_CLOCK pins. This allows the SSC to support many slave-mode
data transfers. In this case, the maximum clock speed allowed on the RX_CLOCK pin is:
– CLK_SSC divided by two if RX_FRAME_SYNC is input.
– CLK_SSC divided by three if RX_FRAME_SYNC is output.
In addition, the maximum clock speed allowed on the TX_CLOCK pin is:
– CLK_SSC divided by six if TX_FRAME_SYNC is input.
– CLK_SSC divided by two if TX_FRAME_SYNC is output.
24.7.2
Transmitter Operations
A transmitted frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured by writing to the TCMR register. See
Section 24.7.4.
The frame synchronization is configured by writing to the Transmit Frame Mode Register
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and
the start mode selected in the TCMR register. Data is written by the user to the Transmit Holding
Register (THR) then transferred to the shift register according to the data format selected.
When both the THR and the transmit shift registers are empty, the Transmit Empty bit is set in
the Status Register (SR.TXEMPTY). When the THR register is transferred in the transmit shift
register, the Transmit Ready bit is set in the SR register (SR.TXREADY) and additional data can
be loaded in the THR register.
Divider
Clock
RX_CLOCK
Transmitter
Clock
MUX
Tri-state
Controller
CKO
Data Transfer
INV
MUX
CKI
Tri-state
Controller
CKG
Receiver
Clock
Output
CKS