594
32072H–AVR32–10/2012
AT32UC3A3
25.7.1
Control Register
Name:
CR
Access Type:
Write-only
Offset:
0x00
Reset Value:
0x00000000
LINWKUP: Send LIN Wakeup Signal
Writing a zero to this bit has no effect.
Writing a one to this bit will send a wakeup signal on the LIN bus.
LINABT: Abort LIN Transmission
Writing a zero to this bit has no effect.
Writing a one to this bit will abort the current LIN transmission.
RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select
Writing a zero to this bit has no effect.
Writing a one to this bit when USART is not in SPI master mode drives RTS high.
Writing a one to this bit when USART is in SPI master mode releases NSS (RTS pin).
RTSEN/FCS: Request to Send Enable/Force SPI Chip Select
Writing a zero to this bit has no effect.
Writing a one to this bit when USART is not in SPI master mode drives RTS low.
Writing a one to this bit when USART is in SPI master mode forces NSS (RTS pin) low, even if USART is not transmitting, in
order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer).
DTRDIS: Data Terminal Ready Disable
Writing a zero to this bit has no effect.
Writing a one to this bit drives DTR high.
DTREN: Data Terminal Ready Enable
Writing a zero to this bit has no effect.
Writing a one to this bit drives DTR low.
RETTO: Rearm Time-out
Writing a zero to this bit has no effect.
Writing a one to this bit reloads the time-out counter and clears CSR.TIMEOUT.
RSTNACK: Reset Non Acknowledge
Writing a zero to this bit has no effect.
Writing a one to this bit clears CSR.NACK.
RSTIT: Reset Iterations
Writing a zero to this bit has no effect.
Writing a one to this bit clears CSR.ITER if ISO7816 is enabled (MR.MODE is 0x4 or 0x6)
31
30
29
28
27
26
25
24
––––––––
23
22
21
20
19
18
17
16
–
LINWKUP
LINABT
RTSDIS/RCS
RTSEN/FCS
DTRDIS
DTREN
15
14
13
12
11
10
9
8
RETTO
RSTNACK
RSTIT
SENDA
STTTO
STPBRK
STTBRK
RSTSTA
76543210
TXDIS
TXEN
RXDIS
RXEN
RSTTX
RSTRX
–