708
32072H–AVR32–10/2012
AT32UC3A3
This bit is cleared when the HBISOFLUSHEC bit disable the HBISOFLUSHI interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
NAKOUTE: NAKed OUT Interrupt Enable
This bit is set when the NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (NAKOUTI).
This bit is cleared when the NAKOUTEC bit is written to one. This will disable the NAKed OUT interrupt (NAKOUTI).
HBISOINERRE: High Bandwidth Isochronous IN Error Interrupt Enable
This bit is set when the HBISOINERRES bit is written to one. This will enable the HBISOINERRI interrupt.
This bit is cleared when the HBISOINERREC bit disable the HBISOINERRI interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
RXSTPE: Received SETUP Interrupt Enable
This bit is set when the RXSTPES bit is written to one. This will enable the Received SETUP interrupt (RXSTPI).
This bit is cleared when the RXSTPEC bit is written to one. This will disable the Received SETUP interrupt (RXSTPI).
UNDERFE: Underflow Interrupt Enable
This bit is set when the UNDERFES bit is written to one. This will enable the Underflow interrupt (UNDERFI).
This bit is cleared when the UNDERFEC bit is written to one. This will disable the Underflow interrupt (UNDERFI).
RXOUTE: Received OUT Data Interrupt Enable
This bit is set when the RXOUTES bit is written to one. This will enable the Received OUT Data interrupt (RXOUT).
This bit is cleared when the RXOUTEC bit is written to one. This will disable the Received OUT Data interrupt (RXOUT).
TXINE: Transmitted IN Data Interrupt Enable
This bit is set when the TXINES bit is written to one. This will enable the Transmitted IN Data interrupt (TXINI).
This bit is cleared when the TXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXINI).