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型號(hào)：	S80C32XXX-16R
廠商：	ATMEL CORP
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, 16 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	82/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S80C32XXX-16R

32072H–AVR32–10/2012

AT32UC3A3

the current access, if no other request is pending, the slave is disconnected from all masters.

This configuration incurs one latency cycle for the first access of a burst. Arbitration without

default master can be used for masters that perform significant bursts.

Round-Robin Arbitration with Last Default Master

This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to

remove the one latency cycle for the last master that accessed the slave. In fact, at the end of

the current transfer, if no other master request is pending, the slave remains connected to the

last master that performed the access. Other non privileged masters still get one latency cycle if

they want to access the same slave. This technique can be used for masters that mainly perform

single accesses.

Round-Robin Arbitration with Fixed Default Master

This is another biased round-robin algorithm. It allows the Bus Matrix arbiters to remove the one

latency cycle for the fixed default master per slave. At the end of the current access, the slave

remains connected to its fixed default master. Every request attempted by this fixed default mas-

ter will not cause any latency whereas other non privileged masters will still get one latency

cycle. This technique can be used for masters that mainly perform single accesses.

Fixed Priority Arbitration

This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to

the same slave by using the fixed priority defined by the user. If two or more master requests are

active at the same time, the master with the highest priority number is serviced first. If two or

more master requests with the same priority are active at the same time, the master with the

highest number is serviced first.

For each slave, the priority of each master may be defined through the Priority Registers for

Slaves (PRAS and PRBS).

Slave and Master assignation

The index number assigned to Bus Matrix slaves and masters are described in Memories

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