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型號：	S80C32XXX-16R
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 16 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁數(shù)：	10/1021頁
文件大?。?/td>	15196K
代理商：	S80C32XXX-16R

32072H–AVR32–10/2012

AT32UC3A3

Fix/Workaround

The LIN ID is not transmitted in mode PDCM='0'

Fix/Workaround

Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first

address of the transmit buffer is not used. The LINID must be written in the LINIR register,

after the configuration and start of the PDCA transfer. Writing the LINID in the LINIR register

will start the transfer whenever the PDCA transfer is ready.

The LINID interrupt is only available for the header reception and not available for the

header transmission

Fix/Workaround

USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set

If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never

Fix/Workaround

Only use PDCM=0 configuration with the PDCA transfer.

The RTS output does not function correctly in hardware handshaking mode

The RTS signal is not generated properly when the USART receives data in hardware hand-

shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output

should go high, but it will stay low.

Fix/Workaround

Do not use the hardware handshaking mode of the USART. If it is necessary to drive the

RTS output high when the Peripheral DMA receive buffer becomes full, use the normal

mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when

the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the

USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-

fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART

CR so that RTS will be driven low.

ISO7816 Mode T1: RX impossible after any TX

RX impossible after any TX.

Fix/Workaround

SOFT_RESET on RX+ Config US_MR + Config_US_CR.

SPI disable does not work in SLAVE mode

SPI disable does not work in SLAVE mode.

Fix/Workaround

Read the last received data, then perform a software reset by writing a one to the Software

Reset bit in the Control Register (CR.SWRST).

SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and

When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one

(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,

then an additional pulse will be generated on SCK.

相關PDF資料	PDF描述
S80C52CXXX-16	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
S80C52CXXX-25SHXXX	8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:D	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:R	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-40SHXXX:RD	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44

相關代理商/技術參數(shù)	參數(shù)描述
S80C376CB8 WAF	制造商:Intel 功能描述:
S80C42	制造商:Intel 功能描述:
S80C51 WAF	制造商:Intel 功能描述:
S80C51-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C51-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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