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參數(shù)資料
| 型號(hào)： | S71WS512N80BAEZZ0 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動(dòng)存儲(chǔ)芯片的CMOS 1.8伏特 |
| 文件頁(yè)數(shù)： | 52/142頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BAEZZ0 |
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52
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
S71WS512NE0BFWZZ_00_ A1 June 28, 2004
A d v a n c e I n f o r m a t i o n
Burst Sequence
Only sequential burst is allowed in the device.
CR7
defaults to a ‘1’ and must al-
ways be set to a ‘1’.
Burst Length Configuration
The device supports four different read modes: continuous mode, and 8, 16, and
32 word linear with or without wrap around modes. A continuous sequence (de-
fault) begins at the starting address and advances the address pointer until the
burst operation is complete. If the highest address in the device is reached during
the continuous burst read mode, the address pointer wraps around to the lowest
address.
For example, an eight-word linear read with wrap around begins on the starting
address written to the device and then advances to the next 8 word boundary.
The address pointer then returns to the 1st word after the previous eight word
boundary, wrapping through the starting location. The sixteen- and thirty-two lin-
ear wrap around modes operate in a fashion similar to the eight-word mode.
Table 15
shows the
CR2-CR0
and settings for the four read modes.
Burst Wrap Around
By default, the device will perform burst wrap around with
CR3
set to a ‘1’.
Changing the
CR3
to a ‘0’ disables burst wrap around.
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising edge of the clock after the
initial synchronous access time. Subsequent outputs will also be on the following
rising edges, barring any delays. The device can be set so that the falling clock
edge is active for all synchronous accesses.
CR6
determines this setting; “1” for
rising active (default), “0” for falling active.
RDY Configuration
By default, the device is set so that the RDY pin will output V
OH
whenever there
is valid data on the outputs. The device can be set so that RDY goes active one
data cycle before active data.
CR8
determines this setting; “1” for RDY active
(default) with data, “0” for RDY active one clock cycle before valid data. In asyn-
chronous mode, RDY is an open-drain output.
RDY Polarity
By default, the RDY pin will always indicate that the device is ready to handle a
new transaction with
CR10
set to a ‘1’ when high. In this case, the RDY pin is
active high. Changing the
CR10
to a ‘0’ sets the RDY pin to be active low. In this
Table 15. Burst Length Configuration
Burst Modes
Address Bits
CR2
CR1
CR0
Continuous
0
0
0
8-word linear
0
1
0
16-word linear
0
1
1
32-word linear
1
0
0
Note:
Upon power-up or hardware reset the default setting is continuous.
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| S71WS512N80BAEZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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| S71WS512N80BAIZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512N80BAEZZ2 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAEZZ3 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ0 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ2 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ3 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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