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參數(shù)資料
| 型號(hào)： | S71WS512N80BAEZZ0 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動(dòng)存儲(chǔ)芯片的CMOS 1.8伏特 |
| 文件頁(yè)數(shù)： | 114/142頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BAEZZ0 |
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114
128Mb pSRAM
S71WS512NE0BFWZZ_00_A1 June 28, 2004
P r e l i m i n a r y
AC CHARACTERISTICS (Continued)
SYNCHRONOUS WRITE OPERATION (BURST MODE)
Notes
*1: Defined from the valid input edge to the High to Low transition of either ADV#, CE#1, or WE#, whichever
occurs last. And once they are determined, they must not be changed until the end of burst.
*2: The output load 50pF with 50ohm termination to V
DDQ
*0.5 V.
*3: Defined from the valid clock edge where last data-in being latched at the end of burst write to the High to
Low transition of either ADV# or CE#1 whichever occurs late for the next access.
*4: Defined from the Low to High transition of CE#1 to the High to Low transition of either ADV# or CE#1
whichever occurs late for the next access.
Parameter
Symbol
Value
Unit
Notes
Min.
Max.
Burst Write Cycle Time
t
WCB
—
8000
ns
Data Setup Time to Clock
t
DSCK
5
—
ns
Data Hold Time from CLK
t
DHCK
3
—
ns
WE# Low Setup Time to 1st Data In
t
WLD
30
—
ns
UB#, LB# Setup Time for Write
t
BS
–5
—
ns
*1
WE# Setup Time to CLK
t
WSCK
5
—
ns
WE# Hold Time from CLK
t
CKWH
5
—
ns
CE#1 Low to WAIT# High
t
CLTH
5
20
ns
*2
WE# Low to WAIT# High
t
WLTH
0
20
ns
*2
CE#1 High to WAIT# High-Z
t
CHTZ
—
20
ns
*2
WE# High to WAIT# High-Z
t
WHTZ
—
20
ns
*2
Burst End CE#1 Low Hold Time from CLK
t
CKCLH
5
—
ns
Burst End CE#1 High Setup Time to next CLK
t
CHCK
5
—
ns
Burst End UB#, LB# Hold Time from CLK
t
CKBH
5
—
ns
Burst Write Recovery Time
t
WRB
26
ns
*3
Burst Terminate Recovery
Time
BL=8,16
t
TRB
26
—
ns
*4
BL=Continuous
t
TRB
70
—
ns
*4
相關(guān)PDF資料 |
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| S71WS512N80BAEZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAEZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512N80BAEZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAEZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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