
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit Flash Family
5
P r e l i m i n a r y
Figures
Figure 2.1
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Figure 4.7
Figure 4.8
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Figure 7.5
Figure 7.6
Figure 8.1
Figure 8.2
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Figure 11.5
Figure 11.6
Figure 11.7
Figure 11.8
Figure 11.9
Figure 11.10
Figure 11.11
Figure 11.12
Figure 11.13
Figure 11.14
Figure 11.15
Logic Symbols – PL256N, PL129N, and PL127N .........................................................7
Connection Diagram – 84-ball Fine-Pitch Ball Grid Array (S29PL256N)..........................9
Physical Dimensions – 84-ball Fine-Pitch Ball Grid Array (S29PL256N) ........................ 10
Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL127N) ....................... 11
Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL129N) ....................... 12
Physical Dimensions – 64-Ball Fine-Pitch Ball Grid Array (S29PL-N) ...........................................13
Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL127N, S29PL256N) ............14
Physical Dimensions – 64-Ball Fortified Ball Grid Array (S29PL-N)..............................................15
MCP Look-Ahead Diagram .................................................................................... 16
Single Word Program Operation ............................................................................ 27
Write Buffer Programming Operation ..................................................................... 30
Sector Erase Operation ........................................................................................ 32
Write Operation Status Flowchart .......................................................................... 39
Simultaneous Operation Block Diagram for S29PL256N and S29PL127N ..................... 43
Simultaneous Operation Block Diagram for S29PL129N ............................................ 44
Advanced Sector Protection/Unprotection ............................................................... 48
Lock Register Program Algorithm........................................................................... 52
Maximum Negative Overshoot Waveform ............................................................... 59
Maximum Positive Overshoot Waveform................................................................. 59
Test Setup ......................................................................................................... 60
Input Waveforms and Measurement Levels............................................................. 61
V
CC
Power-Up Diagram ........................................................................................ 61
Read Operation Timings ....................................................................................... 64
Page Read Operation Timings ............................................................................... 65
Reset Timings..................................................................................................... 65
Program Operation Timings .................................................................................. 67
Accelerated Program Timing Diagram .................................................................... 67
Chip/Sector Erase Operation Timings ..................................................................... 68
Back-to-back Read/Write Cycle Timings ................................................................. 68
Data# Polling Timings (During Embedded Algorithms).............................................. 69
Toggle Bit Timings (During Embedded Algorithms)................................................... 69
DQ2 vs. DQ6 ...................................................................................................... 70