參數(shù)資料
型號: S29PL129N65FFIW00
廠商: Spansion Inc.
英文描述: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述: 256/128/128字節(jié)(16/8/8 M中的x 16位),3.0伏的CMOS只同步讀/寫,頁模式閃存
文件頁數(shù): 55/85頁
文件大?。?/td> 940K
代理商: S29PL129N65FFIW00
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit Flash Family
53
P r e l i m i n a r y
8.6
Advanced Sector Protection Software Examples
Table 8.2
contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the sta-
tus of the sector. In summary, if the PPB Lock Bit is locked (set to
0
), no changes to the PPBs are
allowed. The PPB Lock Bit can only be unlocked (reset to
1
) through a hardware reset or power
cycle. See also
Figure 8.1
for an overview of the Advanced Sector Protection feature.
8.7
Hardware Data Protection Methods
The device offers data protection at the sector level via hardware control:
When WP#/ACC is at V
IL
, the four outermost sectors are locked (device specific).
There are additional methods by which intended or accidental erasure of any sectors can be pre-
vented via hardware means. The following subsections describes these methods:
8.7.1 W P# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors.
This function is provided by the WP#/ACC pin and overrides the previously discussed Sector Pro-
tection/Unprotection method.
If the system asserts V
IL
on the WP#/ACC pin, the device disables program and erase functions
in the
outermost
boot sectors. The outermost boot sectors are the sectors containing both the
lower and upper set of sectors in a dual-boot-configured device.
If the system asserts V
IH
on the WP#/ACC pin, the device reverts to whether the boot sectors
were last set to be protected or unprotected. That is, sector protection or unprotection for these
sectors depends on whether they were last protected or unprotected.
Note that the WP#/ACC pin must not be left floating or unconnected as inconsistent behavior of
the device may result.
The WP#/ACC pin must be held stable during a command sequence execution
8.7.2 Low V
CC
W rite I nhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during
V
CC
power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets
to reading array data. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system
must provide the proper signals to the control inputs to prevent unintentional writes when V
CC
is
greater than V
LKO
.
Table 8.2 Sector Protection Schemes
Unique Device PPB Lock Bit
0 = locked, 1 = unlocked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
Sector Protection Status
Any Sector
0
0
x
Protected through PPB
Any Sector
0
0
x
Protected through PPB
Any Sector
0
1
1
Unprotected
Any Sector
0
1
0
Protected through DYB
Any Sector
1
0
x
Protected through PPB
Any Sector
1
0
x
Protected through PPB
Any Sector
1
1
0
Protected through DYB
Any Sector
1
1
1
Unprotected
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