參數(shù)資料
型號: S29PL129N65FFIW00
廠商: Spansion Inc.
英文描述: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述: 256/128/128字節(jié)(16/8/8 M中的x 16位),3.0伏的CMOS只同步讀/寫,頁模式閃存
文件頁數(shù): 3/85頁
文件大?。?/td> 940K
代理商: S29PL129N65FFIW00
Publication Number
S29PL-N_00
Revision
A
Amendment
4
Issue Date
November 23, 2005
General Description
The Spansion S29PL-N is the latest generation 3.0-Volt page mode read family fabricated using the 110 nm Mirrorbit
TM
Flash process technology. These 8-word page-mode Flash devices are capable of performing simultaneous read and write
operations with zero latency on two separate banks. These devices offer fast page access times of 25 to 30 ns, with
corresponding random access times of 65 ns, 70 ns, and 80 ns respectively, allowing high speed microprocessors to op-
erate without wait states. The S29PL129N device offers the additional feature of dual chip enable inputs (CE1# and
CE2#) that allow each half of the memory space to be controlled separately.
Distinctive Characteristics
Architectural Advantages
32-W ord W rite Buffer
Dual Chip Enable I nputs ( only for S29PL129N)
— Two CE# inputs control selection of each half of the
memory space
Single Pow er Supply Operation
— Full Voltage range of 2.7 – 3.6 V read, erase, and
program operations for battery-powered applications
— Voltage range of 2.7 – 3.1 V valid for PL-N MCP
products
Simultaneous Read/ W rite Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
4-Bank Sector Architecture w ith Top and Bottom
Boot Blocks
256-W ord Secured Silicon Sector Region
— Up to 128 factory-locked words
— Up to 128 customer-lockable words
Manufactured on 0.11 μm Process Technology
Data Retention of 20 years Typical
Cycling Endurance of 100,000 Cycles per Sector
Typical
Performance Characteristics
Hardware Features
W P# / ACC ( W rite Protect/ Acceleration) I nput
— At V
IL
, hardware level protection for the first and last
two 32 Kword sectors.
— At V
IH
, allows the use of DYB/PPB sector protection
— At V
HH
, provides accelerated programming in a
factory setting
Dual Boot and No Boot Options
Low V
CC
W rite I nhibit
Security Features
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors to prevent
program or erase operations within that sector
— Sectors can be locked and unlocked in-system at V
CC
level
Passw ord Sector Protection
— A sophisticated sector protection method locks
combinations of individual sectors to prevent program
or erase operations within that sector using a user
defined 64-bit password
Note:
:
Typical program and erase times assume the following
conditions: 25°C, 3.0 V V
CC
, 10,000 cycles; checkerboard data pattern.
Package Options
VBH064
8.0 x 11.6 mm,
64-ball
256
129
127
S29PL-N MirrorBit Flash Family
S29PL256N, S29PL127N, S29PL129N,
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only
Simultaneous Read/Write, Page-Mode Flash Memory
Data Sheet
PRELIMINARY
Read Access Times ( @ 30 pF, Industrial Temp.)
Random Access Time, ns (t
ACC
)
Page Access Time, ns (t
PACC
)
Max CE# Access Time, ns (t
CE
)
Max OE# Access Time, ns (t
OE
)
65
70
80
25
30
30
65
70
80
25
30
30
Current Consumption ( typical values)
8-Word Page Read
6 mA
Simultaneous Read/Write
65 mA
Program/Erase
25 mA
Standby
20 μA
Typical Program & Erase Times ( typical values) ( See Note)
Typical Word
Typical Effective Word (32 words in buffer)
Accelerated Write Buffer Program
Typical Sector Erase Time (32-Kword Sector)
Typical Sector Erase Time (128-Kword Sector)
40 μs
9.4 μs
6 μs
300 ms
1.6 s
S29PL-N
VBH084
8.0 x 11.6 mm,
84-ball
LAA064
11 x 13 mm, 64-ball
Fortified BGA
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