參數(shù)資料
型號(hào)： S29PL129N65FFIW00
廠商： Spansion Inc.
英文描述： 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述： 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫，頁(yè)模式閃存
文件頁(yè)數(shù)： 24/85頁(yè)
文件大小： 940K
代理商： S29PL129N65FFIW00
22
S29PL-N MirrorBit Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
Legend:
L = Logic Low = V
, H = Logic High = V
,VID = 11.5–12.5 V, V
HH
= 8.5 – 9.5 V,
X = Don’t Care, SA = Sector Address, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1.
The sector and sector unprotect functions may also be implemented by programming equipment.
2.
WP#/ACC must be high when writing to the upper two and lower two sectors.
7.2
Asynchronous Read
The internal state machine is set for reading array data upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. Each bank remains enabled for read access until the command register con-
tents are altered.
7.2.1 Non-Page Random Read
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The
chip enable access time (t
CE
) is the delay from the stable addresses and stable CE# to valid data
at the output inputs. The output enable access time is the delay from the falling edge of the OE#
to valid data at the output (assuming the addresses have been stable for at least t
ACC
– t
OE
time).
7.2.2 Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM
read operation. This mode provides faster read access speed for random locations within a page.
The random or initial page access is t
ACC
or t
CE
and subsequent page read accesses (as long as
the locations specified by the microprocessor falls within that page) is equivalent to t
PACC
. When
CE# is deasserted (= V
IH
), the reassertion of CE# for subsequent access has access time of t
ACC
or t
CE
. Here again, CE# selects the device and OE# is the output control and should be used to
gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by
keeping A
max
– A3 constant and changing A2 – A0 to select the specific word within that page.
Address bits A
max
– A3 select an 8-word page, and address bits A2 – A0 select a specific word
within that page. This is an asynchronous operation with the microprocessor supplying the specific
word location. See
Table 7.3
for details on selecting specific words.
Table 7.2 Dual Chip Enable Device Operation
Operation
CE1#
CE2#
OE#
WE#
RESET#
WP#/ACC
Addresses
(A21 – A0)
DQ15 – DQ0
Read
L
H
L
H
H
X
A
IN
D
OUT
H
L
Write
L
H
H
L
H
X
(
Note 2
)
A
IN
D
IN
H
L
Standby
H
H
X
X
H
X
X
High-Z
Output Disable
L
L
H
H
H
X
X
High-Z
Reset
X
X
X
X
L
X
X
High-Z
Temporary Sector Unprotect
(High Voltage)
X
X
X
X
V
ID
X
A
IN
D
IN
相關(guān)PDF資料
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S29PL129N65FFIW02 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
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S29PL129N65FFIW03 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL129N65FFW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL129N65FFW002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL129N65FFW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
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