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參數(shù)資料
| 型號(hào)： | S29PL127J70 |
| 廠商： | Spansion Inc. |
| 英文描述： | CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | 3.0伏的CMOS只，同步讀/寫閃存與增強(qiáng)VersatileIO控制記憶 |
| 文件頁數(shù)： | 79/106頁 |
| 文件大小： | 1997K |
| 代理商： | S29PL127J70 |
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April 7, 200531107A62
S29PL127J/S29PL129J/S29PL064J/S29PL032J
77
P R E L I M I N A R Y
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# (CE1# / CE2#
for PL129J)
to control the read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates
whether the device is actively erasing, or is in Erase Suspend, but cannot distin-
guish which sectors are selected for erasure. Thus, both status bits are required
for sector and mode information. Refer to
Table 23
to compare outputs for DQ2
and DQ6.
Figure 7
shows the toggle bit algorithm in flowchart form, and the "
DQ2: Toggle
Bit II
" section explains the algorithm. See also the "
DQ6: Toggle Bit I
" section.
Figure 19
shows the toggle bit timing diagram.
Figure 20
shows the differences
between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to
Figure 7
for the following discussion. Whenever the system initially be-
gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
Note:
The system should recheck the toggle bit even if DQ5 = “1” because the toggle
bit may stop toggling as DQ5 changes to “1.” See the "
DQ6: Toggle Bit I
" section and
"
DQ2: Toggle Bit II
" section for more information.
Figure 7.
Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1
No
Yes
Toggle Bit
= Toggle
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Toggle Bit
= Toggle
Read Byte Twice
(DQ7–DQ0)
Address = VA
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
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| S29PL127J70BAI000 | 功能描述:閃存 128Mb 3V 70ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| S29PL127J70BAI020 | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 64FBGA - Trays |
| S29PL127J70BFI000 | 制造商:Spansion 功能描述:SPZS29PL127J70BFI000 POWER MOSFET 30 V, 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 80FBGA - Trays |
| S29PL127J70TAI130 | 制造商:Spansion 功能描述: 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Trays |
| S29PL127J70TFI130 | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Trays |
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