參數(shù)資料
型號: S29PL127J70
廠商: Spansion Inc.
英文描述: CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
中文描述: 3.0伏的CMOS只,同步讀/寫閃存與增強(qiáng)VersatileIO控制記憶
文件頁數(shù): 66/106頁
文件大?。?/td> 1997K
代理商: S29PL127J70
64
S29PL127J/S29PL129J/S29PL064J/S29PL032J
31107A62 April 7, 2005
P R E L I M I N A R Y
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations.
Table 21
defines the valid register command
sequences. Writing
incorrect
address and data values
or writing them in the
improper sequence
may place the device in an unknown state. A reset com-
mand is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE# (CE1# / CE2# in
PL129J), whichever happens later. All data is latched on the rising edge of WE#
or CE# (CE1# / CE2# in PL129J), whichever happens first. Refer to the "
AC Char-
acteristic
" section section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. The system can read
array data using the standard read timing, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing
a programming operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See the "
Erase Suspend/Erase
Resume Commands
" section section for more information.
The system
must
issue the reset command to return a bank to the read (or
erase-suspend-read) mode if DQ5 goes high during an active program or erase
operation, or if the bank is in the autoselect mode. See the next section, "
Reset
Command
" section, for more information.
See also "
Requirements for Reading Array Data
" section in the "
Device Bus Op-
erations
" section section for more information. The "
AC Characteristic
" section
table provides the read parameters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the bank to which
the system was writing to the read mode. If the program command sequence is
written to a bank that is in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If a bank entered the autoselect mode while
in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode.
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