- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374664 > S29PL127J70 (Spansion Inc.) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control PDF資料下載
參數(shù)資料
| 型號： | S29PL127J70 |
| 廠商： | Spansion Inc. |
| 英文描述： | CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | 3.0伏的CMOS只，同步讀/寫閃存與增強VersatileIO控制記憶 |
| 文件頁數(shù)： | 69/106頁 |
| 文件大?。?/td> | 1997K |
| 代理商： | S29PL127J70 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁當前第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
April 7, 200531107A62
S29PL127J/S29PL129J/S29PL064J/S29PL032J
67
P R E L I M I N A R Y
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does
not
require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations.
Table 21
shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the "
Write
Operation Status" section
section for information on these status bits.
Any commands written during the chip erase operation are ignored.
Note that
SecSi Sector, autoselect, and CFI functions are unavailable when a [pro-
gram/erase] operation is in progress.
However, note that a
hardware reset
immediately terminates the erase operation. If that occurs, the chip erase com-
mand sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
5 illustrates the algorithm for the erase operation. Refer to the "
Erase/Program
Operations
" section tables in the AC Characteristics section for parameters, and
Figure 16
section for timing diagrams.
Note:
See
Table 21
for program command sequence.
Figure 4.
Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S2A_1 | 2.0 AMPS. Surface Mount Rectifiers |
| S2K | 2.0 AMPS. Surface Mount Rectifiers |
| S2M | 2.0 AMPS. Surface Mount Rectifiers |
| S2A | 2.0 AMPS. Surface Mount Rectifiers |
| S2B | 2.0 AMPS. Surface Mount Rectifiers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29PL127J70BAI000 | 功能描述:閃存 128Mb 3V 70ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| S29PL127J70BAI020 | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 64FBGA - Trays |
| S29PL127J70BFI000 | 制造商:Spansion 功能描述:SPZS29PL127J70BFI000 POWER MOSFET 30 V, 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 80FBGA - Trays |
| S29PL127J70TAI130 | 制造商:Spansion 功能描述: 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Trays |
| S29PL127J70TFI130 | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。