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參數(shù)資料
| 型號： | S29NS064N0PBJW003 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封裝： | 7.70 X 6.20 MM, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 59/86頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | S29NS064N0PBJW003 |
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S29NS-N_00_A12 June 13, 2006
S29NS-N MirrorBit Flash Family
57
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
12.2
RDY: Ready
The RDY pin is a dedicated status output that indicates valid output data on A/DQ15–A/DQ0 during burst
(synchronous) reads. When RDY is asserted (RDY = V
OH
), the output data is valid and can be read. When
RDY is de-asserted (RDY = V
OL
), the system should wait until RDY is re-asserted before expecting the next
word of data.
In synchronous (burst) mode with CE# = OE# = V
IL
, RDY is de-asserted under the following conditions:
during the initial access; after crossing the internal boundary between addresses 7Eh and 7Fh (and
addresses offset from these by a multiple of 64). The RDY pin will also switch during status reads when a
clock signal drives the CLK input. In addition, RDY = V
OH
when CE# = V
IL
and OE# = V
IH
, and RDY is Hi-Z
when CE# = V
IH
.
In asynchronous (non-burst) mode, the RDY pin does not indicate valid or invalid output data. Instead, RDY =
V
OH
when CE# = V
IL
, and RDY is Hi-Z when CE# = V
IH
.
12.3
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the
same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. Note that OE# must be low during toggle bit status reads. When the operation is complete,
DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately t
ASP
, all sectors protected toggle time, then returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on
DQ7: Data# Polling
on page 55
).
If a program address falls within a protected sector, DQ6 toggles for approximately t
PSP
after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
algorithm is complete.
See the following for additional information: (toggle bit flowchart),
DQ6: Toggle Bit I
on page 57
(description),
Figure 19.10 on page 73
(toggle bit timing diagram), and
Table 12.1 on page 59
(compares DQ2 and DQ6).
12.4
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure.
Note that OE# must be low during toggle bit status reads. But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing,
or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits
are required for sector and mode information. Refer to
Table 12.2 on page 60
to compare outputs for DQ2
and DQ6.
See the following for additional information: (toggle bit flowchart),
DQ6: Toggle Bit I
on page 57
(description),
Figure 19.10 on page 73
(toggle bit timing diagram), and
Table 12.1 on page 59
(compares DQ2 and DQ6).
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