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參數(shù)資料
| 型號(hào)： | S29NS064N0PBJW003 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封裝： | 7.70 X 6.20 MM, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 41/86頁 |
| 文件大小： | 1036K |
| 代理商： | S29NS064N0PBJW003 |
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S29NS-N_00_A12 June 13, 2006
S29NS-N MirrorBit Flash Family
39
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
10.3.8
RDY Polarity
By default, the RDY pin will always indicate that the device is ready to handle a new transaction with
CR10
set to a ‘1’. In this case, the RDY pin is active high. Changing the
CR10
to a ‘0’ sets the RDY pin to be active
low. In this case, the RDY pin will always indicate that the device is ready to handle a new transaction when
low.
11. Configuration Register
Table 11.1
shows the address bits that determine the configuration register settings for various device
functions.
Notes
1. Device will be in the default state upon power-up or hardware reset.
2. CR3 will always equal to 1 (Wrap around mode) when CR0,CR1,CR2 = 000 (continuous Burst mode).
3. A software reset command is required after a read or write command.
11.1
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t
cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the bank to which the system was writing to the read mode.
Once erasure
begins, however, the device ignores reset commands until the operation is complete
.
The reset command may be written between the sequence cycles in a program command sequence before
programming begins. This resets the bank to which the system was writing to the read mode. If the program
command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode.
Once programming begins, however, the device
ignores reset commands until the operation is complete
.
Table 11.1
Configuration Register
CR BIt
Function
Settings (Binary)
CR15
Reserved
0 = Default
CR14
Reserved
0 = Default
CR13
Programmable
Wait State
000 = Data is valid on the 2nd active CLK edge after AVD# transition to V
IH
001 = Data is valid on the 3rd active CLK edge after AVD# transition to V
IH
010 = Data is valid on the 4th active CLK edge after AVD# transition to V
IH
011 = Data is valid on the 5th active CLK edge after AVD# transition to V
IH
100 = Data is valid on the 6th active CLK edge after AVD# transition to V
IH
101 = Data is valid on the 7th active CLK edge after AVD# transition to V
IH
(default)
110 = Reserved
111 = Reserved
CR12
CR11
CR10
RDY Polarity
0 = RDY signal is active low
1 = RDY signal is active high (default)
CR9
Reserved
1 = Default
CR8
RDY
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
CR7
Reserved
1 = default
CR6
Reserved
1 = default
CR5
Reserved
0 = default
CR4
Reserved
0 = default
CR3
Burst Wrap Around
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
CR2
Burst Length
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
CR1
CR0
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