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參數(shù)資料
| 型號： | S29NS064N0PBJW003 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封裝： | 7.70 X 6.20 MM, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 50/86頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | S29NS064N0PBJW003 |
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48
S29NS-N MirrorBit Flash Family
S29NS-N_00_A12 June 13, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
11.12 Password Protection Command Set Definitions
The Password Protection Command Set permits the user to program the 64-bit password, verify the
programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password.
The
Password Protection Command Set Entry
command sequence must be issued prior to any of the
commands listed following to enable proper command execution.
Note that issuing the Password Protection Command Set Entry command disables reads and writes for Bank
0. Reads for other banks excluding Bank 0 are allowed.
However Writes to any bank are not allowed.
Password Program Command
Password Read Command
Password Unlock Command
The Password Program Command permits programming the password that is used as part of the hardware
protection scheme. The actual password is 64-bits long. There is no special addressing order required for
programming the password.
Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent
verification. The Password Program Command is only capable of programming “0”s. Programming a “1” after
a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm with the cell
remaining as a “0”. The password is all 1’s when shipped from the factory. All 64-bit password combinations
are valid as a password.
The Password Verify Command is used to verify the Password. The Password is verifiable only when the
Password Mode Lock Bit is not programmed. If the Password Mode Lock Bit is programmed and the user
attempts to verify the Password, the device will always drive all 1’s onto the DQ data bus.
The lower two address bits (A1–A0) are valid during the Password Read, Password Program, and Password
Unlock.
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for
modification, thereby allowing the PPBs to become accessible for modification. The exact password must be
entered in order for the unlocking function to occur. This command cannot be issued any faster than 1 μs at a
time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a
password. If the command is issued before the 1 μs execution window for each portion of the unlock, the
command will be ignored.
The Password Unlock function is accomplished by writing Password Unlock command and data to the device
to perform the clearing of the PPB Lock Bit. The password is 64 bits long. A1 and A0 are used for matching.
Writing the Password Unlock command does not need to be address order specific. An example sequence is
starting with the lower address A1–A0= 00, followed by A1–A0= 01, A1–A0= 10, and A1–A0= 11.
Approximately 1 μs is required for unlocking the device after the valid 64-bit password is given to the device.
It is the responsibility of the microprocessor to keep track of the entering the portions of the 64-bit password
with the Password Unlock command, the order, and when to read the PPB Lock bit to confirm successful
password unlock. In order to re-lock the device into the Password Mode, the PPB Lock Bit Set command can
be re-issued.
The
Password Protection Command Set Exit
command must be issued after the execution of the
commands listed previously to reset the device to read mode, otherwise the device will hang. Note that
issuing the
Password Protection Command Set Exit
command re-enables reads and writes for Bank 0.
相關(guān)PDF資料 |
PDF描述 |
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| S29NS064N0SBJW000 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS064N0SBJW002 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS064N0SBJW003 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0PBJW000 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0PBJW002 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS064N0SBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS064N0SBJW002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS064N0SBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128J0LBAW00 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| S29NS128J0LBAW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories |
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