- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365399 > S29NS064N0PBJW003 (SPANSION LLC) Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory PDF資料下載
參數(shù)資料
| 型號： | S29NS064N0PBJW003 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封裝： | 7.70 X 6.20 MM, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 57/86頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | S29NS064N0PBJW003 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁當前第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
S29NS-N_00_A12 June 13, 2006
S29NS-N MirrorBit Flash Family
55
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the
autoselect mode, or if DQ5 goes high (while the bank is providing status information).
9. The fourth cycle of the autoselect command sequence is a read cycle. The system must read device IDs across the 4th, 5th, and 6th cycles, The system must
provide the bank address. See the
Autoselect Command Sequence
section for more information.
10.
See
Table 11.2 on page 40
for description of bus operations.
11.See the Autoselect Command Sequence
on page 40
.
12.The Unlock Bypass command sequence is required prior to this command sequence.
13.The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.
14.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is
valid only during a sector erase operation, and requires the bank address.
15.The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.
16.Command is valid when device is ready to read array data or when device is in autoselect mode.
17.The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the
command sequence is 37.
18.The entire four bus-cycle sequence must be entered for which portion of the password.
19.The ALL PPB ERASE command will pre-program all PPBs before erasure to prevent over-erasure of PPBs.
20.Command sequence resets device for next command after write-to-buffer operation.
21.Entry commands are needed to enter a specific mode to enable instructions only available within that mode.
22.Write Buffer Programming can be initiated after Unlock Bypass Entry.
23.If both the Persistent Protection Mode Locking Bit and the password Protection Mode Locking Bit are set a the same time, the command operation will abort and
return the device to the default Persistent Sector Protection Mode.
24.The Exit command must be issued to reset the device into read mode. Otherwise the device will hang.
25.Note: Autoselect, CFI, OTP, Unlock Bypass Mode and all ASP modes cannot be nested with each other.
26.Only A7 - A0 (lower address bits) are used
27.A
max
–A0 (all address bits) are used.
28.Requires the RESET# command to configure the configuration register.
29.See
Figure 11.4 on page 50
for details.
12. Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7.
Table 12.2 on page 60
and the following subsections describe the function of these bits. DQ7
and DQ6 each offers a method for determining whether a program or erase operation is complete or in
progress.
12.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence.
Note that the Data# Polling is valid only for the
last word being programmed in the write-buffer-page during Write Buffer Programming. Reading
Data# Polling status on any word other than the last word to be programmed in the write-buffer-page
will return false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately t
PSP
, then that bank returns to the read
mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately t
ASP
, then the bank returns to the read mode. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors
that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may
not be valid.
相關PDF資料 |
PDF描述 |
|---|---|
| S29NS064N0SBJW000 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS064N0SBJW002 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS064N0SBJW003 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0PBJW000 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0PBJW002 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS064N0SBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS064N0SBJW002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS064N0SBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128J0LBAW00 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| S29NS128J0LBAW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories |
發(fā)布緊急采購，3分鐘左右您將得到回復。