參數(shù)資料
型號(hào)： S29NS064N0PBJW003
廠商： SPANSION LLC
元件分類(lèi)： DRAM
英文描述： Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
封裝： 7.70 X 6.20 MM, LEAD FREE, FBGA-44
文件頁(yè)數(shù)： 46/86頁(yè)
文件大?。?/td> 1036K
代理商： S29NS064N0PBJW003
44
S29NS-N MirrorBit Flash Family
S29NS-N_00_A12 June 13, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Figure 11.2
Write Buffer Programming Operation
11.7
Chip Erase Command Sequence
11.7.1
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
Table 11.4 on page 52
shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer
to
Write Operation Status
on page 55
for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a
hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array data, to ensure data integrity.
Write “Write to Buffer”
command and
Sector Address
Write number of addresses
to program minus 1(WC)
and Sector Address
Write program buffer to
flash sector address
Write first address/data
Write to a different
sector address
FAIL or ABORT
PASS
Read DQ15 - DQ0 at
Last Loaded Address
Read DQ15 - DQ0 with
address = Last Loaded
Address
Write next address/data pair
WC = WC - 1
WC = 0
Part of “Write to Buffer”
Command Sequence
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Abort Write to
Buffer Operation
DQ7 = Data
DQ7 = Data
DQ5 = 1
DQ1 = 1
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
to read mode.
相關(guān)PDF資料
PDF描述
S29NS064N0SBJW000 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29NS064N0SBJW000 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS064N0SBJW002 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS064N0SBJW003 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128J0LBAW00 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS128J0LBAW000 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Burst Mode Flash Memories
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