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參數(shù)資料
| 型號： | S1R72803F00A100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 0.40 MM PITCH, PLASTIC, QFP20-184 |
| 文件頁數(shù)： | 90/115頁 |
| 文件大?。?/td> | 833K |
| 代理商： | S1R72803F00A100 |
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S1R72803F00A
72
EPSON
Address
Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x51
BufMonitor
7: RxPayldRdy
R
0: Rx Payld Capa not Ready 1: Rx Payload Capa Ready
6: TxPayldRdy
R
0: Tx Payld Capa not Ready
1: Tx Payload Capa Ready
5:
0:
1:
4: TxStreamFull
R
0: NotFull
1: Full
0x00
–
3: RxHdrRemain
R
0: Rx Header Area Empty
1: Rx Header not Empty
2: RxORBFull
R
0: Rx ORB Area not Full
1: Rx ORB Data Area Full
1: RxStreamFull
R
0: Rx Stream Area not Full
1: Rx Stream Data Area Full
0: RxHdrFull
R
0: Rx Header Area not Full
1: Rx Header Area Full
Buffer Monitor Register
This Buffer Monitor Register indicates each buffer area status.
This register is read-only. Writing to this register is ignored..
bit7 Rx Payload Ready
When a free space the equivalent of the size set by the PyloadSize Register exists in the RxStreamArea, this bit
becomes “1”. When not, this bit becomes “0”.
bit6 Tx Payload Ready
When transmit data the equivalent of the size set by the PayloadSize Register is accumulated in the
RxStreamArea, this bit becomes “1”. When not, this bit becomes “0”.
bit5 Reserved
bit4 TxStreamFull
This bit indicates the status of the transmitting stream buffer. This bit becomes “1” when the buffer is full, and
“0” in other statuses.
bit3 Received Header Remain
When an unused packet header exists in the header area of a receive packet, this bit becomes “1”.
When the firmware rewrites the UsedRxHdrPtr to one same as LINKRxHdrPtr or when you write “1” to the
BufControl.RxHdrCtr bit, this bit becomes “0”.
Bit2 Received ORB Data Full
When the ORB buffer area of receive packet data is full of received data, this bit becomes “1”. The firmware
must turn on RxDMACtl.ForceBusy bit if this bit is turned on to give priority to the processing to free the buffer
by starting a processing with the first received packet immediately. When the receive buffer area is freed, the
RxDMACtl.ForceBusy is cleared.
Bit1 Received Stream Data Full
When the stream buffer area of receive packet data is full of received data, this bit becomes “1”. The firmware
must turn on the RxDMACtl.ForceBusy bit if this bit is turned on to give priority to the processing to free the
buffer by starting a processing with the first received packet immediately. When the receive buffer area is freed,
the RxDMACtl.ForceBusy is cleared.
Bit0 Received Header Full
When the header area of receive packet data is full, this bit becomes “1”. The firmware must turn on the
RxDMACtl.ForceBusy bit if this bit is turned on to give priority to the processing to free the buffer by starting
a processing with the first received packet immediately. When the receive buffer area is freed, the
RxDMACtl.ForceBusy is cleared.
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