參數(shù)資料
型號(hào): S1R72803F00A100
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 0.40 MM PITCH, PLASTIC, QFP20-184
文件頁數(shù): 72/115頁
文件大小: 833K
代理商: S1R72803F00A100
S1R72803F00A
2
EPSON
q Built-in CPU
Integration of a CPU eliminated the necessity of an
external CPU to control this IC.
CPU core:
32-bit RISC CPU S1C33000
Harvard architecture (Concurrency
of a fetch and load/store)
High speed/high performance:
Ready for operation with 25MHz
Command set: 16-bit fixed length, 105 types of basic
commands
Execution cycle:
Execution at one cycle/command
regarding a main command
AND/OR (MAC) operation:
16 bits
× 16 bits + 64 bits, 2 clocks/
MAC
CPU Register: 16 32-bit general registers and 5 32-
bit special registers
Memory space:Linear space where 256-Mbyte (28-
bit) code, data, and I/O can be
mapped.
External bus interface:
Directly connects the external
memory of the memory area.
Programmable wait cycle (7 cycles,
Max.)
Enables handshake through the
XWAIT terminal.
Interrupt:
Ready for reset, NMI, max. 128
external interrupts, 4 software
interrupts, and 2 exceptions
Reset, boot:
Cold reset, hot reset
Built-in RAM: 8Kbytes for work
q Flash ROM
Integration of a Flash ROM eliminated the necessity
of a ROM to externally store programs.
Memory structure:
Memory size 512K (32K
× 16) bits
Sector size:
512 words/sector
Unit of erase: Per chip or sector
Unit of write: Writing with words
Erase/write time:
Chip erase time 100ms (Standard)
Sector erase time 20ms (Standard)
Write time:
15
s (Standard)
Access time:
90nsec. (Max.)
Reliability:
No. of erase/write 1,000 times
Data retention: 10 years
q Others
A Boot ROM (4MBbytes, Max.) is connectable to
outside of this IC.
Supply voltage, 5.0V
± 10% and 3.3V ± 0.3V
184PinQFP (0.4mm pitch)
Not radiation resistant.
The CPU core built into this IC is an original 32-bit
RISC CPU from SEIKO EPSON. Regarding the CPU
core, refer to the S1C33208/204/202 Technical Manual
and S1C33 Family ASIC Macro Manual. The built-in
RAM is 8Kbytes.
Note: In the built-in CPU core, a DMA controller and
A/D converter are not integrated; this part is
different from the description on the DMA
controller and A/D converter given in Technical
Manual (and Macro Manual). A low speed
oscillation circuit (OSC1) is not available.
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