參數(shù)資料
型號： S1D13700F02A100
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64
封裝： LEAD FREE, TQFP-64
文件頁數(shù)： 97/108頁
文件大?。?/td> 1373K
代理商： S1D13700F02A100
5: SPECIFICATIONS
84
EPSON
S1D13700 Technical Manual
5.3
Electrical Characteristics
[VSS = 0V, HVDD = 4.5 – 5.5V, Ta = -40 – 85°C]
Note: 1. The pulse applied to the RESET# pin must be held low for 200
s or more to be effective.
However, avoid keeping the input pulse active for more than several seconds because the
LCD’s d.c. drive capability may be adversely affected.
2. The VB0–DB7 pins come with a feedback circuit, so that even when input becomes high im-
pedance, the pins retain the state held immediately before. Therefore, input voltage of an in-
termediate level allows input current to ow to the pin.
Parameter
Symbol
Test Condition
Rated Value
Unit
Min.
Typ.
Max.
Input Leakage Current
OFF-state Leakage Current
ILI
IOZ
—
—Note 2)
-1
—
1
uA
High Level Output Voltage
VOH
IOH = -8.0mA
HVDD=Min
HVDD-0.4
——
V
Low Level Output Voltage
VOL
IOL = 8.0m
HVDD=Min
——
0.4
V
High Level Input Voltage
VIH1
CMOS level
HVDD = Max
3.5
——
V
Low Level Input Voltage
VIL1
CMOS level
HVDD = Min
——
1.0
V
Positive Trigger Voltage
VT1+
CMOS Schmitt
2.0
—
4.0
V
Negative Trigger Voltage
VT1-
CMOS Schmitt
0.8
—
3.1
V
Hysteresis Voltage
VH1
CMOS Schmitt
0.3
——
V
High Level Input Voltage
VIH2
TTL level
HVDD = Max
2.0
——
V
Low Level Input Voltage
VIL2
TTL level
HVDD = Min
——
0.8
V
Pulldown Resistance
RPD
VI = HVDD
30
60
144
k
Operating Supply Current
Iopr
fOSC =10 MHz
Nonloaded
256 x 200dot
—
TBD
mA
Quiescent Supply Current
(between HVDD and VSS)
IQH
Sleep mode
XCG1, CS#, RD# = VDD
——
30
uA
Quiescent Supply Current
(between LVDD and VSS)
IQH
Sleep mode
XCG1, CS#, RD# = VDD
——
35
uA
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