參數(shù)資料
型號(hào)： S1D13700F02A100
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64
封裝： LEAD FREE, TQFP-64
文件頁(yè)數(shù)： 12/108頁(yè)
文件大?。?/td> 1373K
代理商： S1D13700F02A100
2: PINS
6
EPSON
S1D13700 Technical Manual
2.1.2
Pin Description
Key :
I
=
Input
O
=
Output
IO
=
Input/output
P
=
Power supply
HIBC
=
CMOS input
HIBH
=
CMOS Schmitt input
HIBCD1 =
CMOS input with pulldown resistor (60 ohms typ. at 5.0 V)
HOB2T
=
Normal buffer (8 mA/-8 mA at 5 V)
HBC2T
=
LVTTL I/O buffer (6 mA/-6 mA at 3.3 V)
HTB2T
=
Tri-state output (6 mA/-6 mA at 3.3 V)
HLIN
= Transparent input
HLOT
= Transparent output
ITST1
=
Test mode control input with pulldown resistor (50 ohms typ. at 3.3 V)
Pin Name
Pin No.
I/O
Type
I/O Voltage
I/O Cell
RESET#
State
Description
HIOVDD(VDD)
7 48 55
P
HIOVDD
—
Power supply for host interface
NIOVDD(VDD)
22 32
P
NIOVDD
—
Power supply for LCD interface
COREVDD(VDD)
12 25 40
P
COREVDD
—
Power supply for core logic
VSS
1 17 28 33 53
P
VSS
—
Ground
CLKI
39
I
HIOVDD
HIBH
—
Externally sourced system clock
XCG1(XG)
35
I
HIOVDD
HLOT
—
Gate input for oscillator
XCD1(XD)
34
O
HIOVDD
HLIN
—
Drain output for oscillator
CNF0 – CNF4
(SEL0 – SEL4)
56-60
I
HIOVDD
HIBH
0
Input pin for S1D13700 settings
DB0 – DB7
(D0 – D7)
44-47 49-52
IO
HIOVDD
HBC2T
Hi-Z
Data bus for MPU interface
AB0 – AB15
(A0 – A15)
2-6 8-11 13-16
I
HIOVDD
HIBC
0
Address bus for MPU interface
RD#
41
I
HIOVDD
HIBH
1
Read strobe for MPU interface
WR#
42
I
HIOVDD
HIBH
1
Write strobe for MPU interface
CS#
43
I
HIOVDD
HIBH
1
Chip select for MPU interface
WAIT#
54
O
HIOVDD
HOB2T
Hi-Z
Wait output for MPU interface
AS#
61
I
HIOVDD
HIBC
1
Address strobe for MPU
interface
FPDAT0 –
FPDAT3(XD0 – XD3)
18-21
O
NIOVDD
HOB2T
X
Data bus for X driver
FPSHIFT(XSCL)
23
O
NIOVDD
HOB2T
X
Shift clock for X driver
XECL
24
O
NIOVDD
HOB2T
X
X driver enable chain clock
FPLINE(LP)
26
O
NIOVDD
HOB2T
X
Latch pulse
MOD(WF)
27
O
NIOVDD
HOB2T
X
Frame signal
YSCL
29
O
NIOVDD
HOB2T
X
Scan shift clock
FPFRAME (YD)
30
O
NIOVDD
HOB2T
X
Scan start pulse
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