參數(shù)資料
型號: S1D13700F02A100
元件分類: 顯示控制器
英文描述: 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64
封裝: LEAD FREE, TQFP-64
文件頁數(shù): 23/108頁
文件大?。?/td> 1373K
代理商: S1D13700F02A100
3: COMMANDS AND COMMAND REGISTERS
16
EPSON
S1D13700 Technical Manual
*1 To ensure that two bytes are set at the same time, the low-order byte is xed when the high-order byte is written.
*2 SLEEPIN = 0: Clock enable
Using the internal oscillator circuit causes the oscillator to start oscillating. Using an externally sourced
clock causes the clock to propagate to the internal circuits.
The internal timing circuit is released from reset status by writing to any register after setting SLEEPIN
= 0. (Therefore, internal SRAM cannot be accessed until that time.)
*3 CSRW: Write only (00h when read), CSRR: read only (write invalid).
Other registers can be written to or read from (in units of bits).
The following shows the relationship between memory and register maps in the S1D13700.
* The S1D13700 ignores any attempt to access address space 8030h–FFFFh. This address space may be employed as
a user area, but because there is no negate output available for the WAIT# pin of the S1D13700, inhibit access to this
address space when not in use.
0 x 8019
0 x 00
r_P1_
CGRAMAdr
SAGL
A7
SAGL
A6
SAGL
A5
SAGL
A4
SAGL
A3
SAGL
A2
SAGL
A1
SAGL
A0
0 x 801A *1
0 x 00
r_P2_
CGRAMAdr
SAGH
A15
SAGH
A14
SAGH
A13
SAGH
A12
SAGH
A11
SAGH
A10
SAGH
A9
SAGH
A8
0 x 801B
0 x 00
r_P1_HdotScr
00000
D2
D1
D0
0 x 801C *3
0 x 00
r_P1_CSRW
CSRL
A7
CSRL
A6
CSRL
A5
CSRL
A4
CSRL
A3
CSRL
A2
CSRL
A1
CSRL
A0
0 x 801D *3
0 x 00
r_P2_CSRW
CSRH
A15
CSRH
A14
CSRH
A13
CSRH
A12
CSRH
A11
CSRH
A10
CSRH
A9
CSRH
A8
0 x 801E *3
0 x 00
r_P1_CSRR
CSRL
A7
CSRL
A6
CSRL
A5
CSRL
A4
CSRL
A3
CSRL
A2
CSRL
A1
CSRL
A0
0 x 801F *3
0 x 00
r_P2_CSRR
CSRH
A15
CSRH
A14
CSRH
A13
CSRH
A12
CSRH
A11
CSRH
A10
CSRH
A9
CSRH
A8
0 x 8020
0 x 00
r_P1_
GrayScale
000000
BPP1
BPP0
Address
Hard
Reset
Register name
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
S1D13700 Memory Mapping (AB15 – AB0)
Display RAM
Area
Register Area
0x8021 – 0x802F Reserve
(CGROM Area)
Not Use
(MSB DB7 – LSB DB0)
0000h
7FFFh
8000h
802Fh
85AFh
8030h
85B0h
FFFFh
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