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參數(shù)資料
| 型號(hào)： | S1D13700F02A100 |
| 元件分類： | 顯示控制器 |
| 英文描述： | 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64 |
| 封裝： | LEAD FREE, TQFP-64 |
| 文件頁數(shù)： | 19/108頁 |
| 文件大?。?/td> | 1373K |
| 代理商： | S1D13700F02A100 |
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2: PINS
S1D13700 Technical Manual
EPSON
13
2.2.4
LCD Driver Control Pins
The S1D13700 can directly control both the X and Y drivers based on an enable chain, which is a method of
effectively reducing the amount of current consumption needed to drive dot-matrix liquid crystal display
elements.
Note 5: The YDIS signal goes low at a time equivalent to one to two frames after the sleep command is
written. When the YDIS signal goes low, all Y driver outputs are forcibly brought to an
intermediate level (unselected), thus causing display to turn off. Therefore, to power off the
LCD unit, the liquid crystal drive power supply (with relatively large steady-state current) must
be turned off at the same time display is turned off by using the YDIS signal.
2.2.5
TEST Control Pins
FPDAT0 –
FPDAT3
Output, active high
This 4-bit dot data bus for the X driver (column driver) is connected to the data input pins of the X driver.
FPSHIFT
Output, falling edge triggered
This signal causes the dot data bus signals (FPDAT0–FPDAT3) to be stored in the X driver at the signal’s
falling edge, and thus functions as a shift clock for the internal shift register of the X driver.
To reduce power consumption, this clock is turned off until the MPU starts sending data for the next display
line after outputting the LP signal. (For details, see Section 5.4.4 “LCD Control Signal Timing
XECL
Output, falling edge triggered
XECL is a dedicated clock signal for the X drivers cascaded by an enable chain. It causes the enable signal
to be successively passed to the next X driver every 16 XSCL periods.
FPLINE
Output, falling edge triggered
For the liquid crystal display elements to be successively driven, the X driver contains a circuit to latch each
output bit of the internal shift register at the falling edge of LP. This signal is output for every display line.
MOD
Output
This signal provides a one-frame interval for the X and Y drivers to determine the AC drive waveform for
the LCD panel. Two types of cyclic signals are output depending on how the System Set command
parameters are set.
YSCL
Output, active high, rising edge triggered
This signal is a clock for the Y driver, and is equivalent to XSCL for the X driver. The Y data signal (YD) is
stored in the Y driver at the beginning of a frame, and YSCL is used as an internal shift clock.
FPFRAME
Output, active high
YD is data for the Y driver, and is a cyclic signal output at the first display line interval of a frame. The
electrodes on the common side of liquid crystal display elements are sequentially scanned as the YD signal
is sequentially shifted inside the Y driver synchronously with the YSCL signal.
YDIS
Output, active high
This signal is used to power down the LCD unit and is held high during the display period.
Note 5
TESTEN
Input, active high
Test-enable input used only for production testing (with type-1 pulldown resistor, 50 ohms typ. at 3.3 V).
SCANEN
Input, active high
Test-enable input used only for production testing (with type-1 pulldown resistor, 50 ohms typ. at 3.3 V).
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