參數(shù)資料
型號(hào)： S1D13700F02A100
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64
封裝： LEAD FREE, TQFP-64
文件頁(yè)數(shù)： 16/108頁(yè)
文件大小： 1373K
代理商： S1D13700F02A100
2: PINS
10
EPSON
S1D13700 Technical Manual
2.2.3
System Bus Connecting Pins
Note 3: Normally, CNF2 and CNF3 should be corrected directly to power supply VDD or VSS to prevent
the mixture of noise. Should noise be mixed in, insert a capacitor between the CNF2 and
CNF3 lines and VSS, as close to the IC pins as possible. This will help to effectively eliminate
noise.
DB0 – DB7
Tristate input/output, active high
These pins comprise an 8-bit bidirectional data bus, which is connected to the 8-bit or 16-bit MPU data bus.
CNF2
CNF3
Input, active high
The S1D13700 allows the MPU interface format to be changed depending on how CNF2 and CNF3 are set,
so that it can be connected directly to the 80-series MPU (e.g., Z80 or GenericBus), 68-series MPU (6809
or 6802), or the MC68K-series MPU (68000) bus.
AB15 – AB1
AB0
Input, active high
Normally, the MPU address bus is connected to these pins. The data bus signal is discriminated by a combi-
nation of RD# and WR# signals, or R/W#, E, and LDS signals, as listed in the table below.
CMF4
Input: CNF4 = 0 selects direct access; CNF4 = 1 selects indirect access.
<Direct access for the 80-series interface>
<Indirect access for the 80-series interface>
CNF3
CNF2
Mode
AB15
– AB1
AB0
RD#
WR#
CS#
DB7
– DB0
WAIT#
AS#
0
80 series
↑↑↑↑↑↑
↑
–
01
*
******
**
1
0
6800
↑↑
E
R/W#
↑↑
––
1
MC68K
↑↑
LDS#
R/W#
↑↑
DTACK#
↑
Settings marked with * are inhibited.
Note 3
CNF4
AB15
– AB1
AB0
RD#
WR#
Function
0
0or1
0
1
Read from command/parameter
registers
0
0or1
1
0
Write to command/parameter registers
*AB15–AB0 are used as register addresses.
CNF4
AB15
– AB1
AB0
RD#
WR#
Function
1–001
–
1–101
Data (display data and cursor address)
read
1–010
Data (display data and parameter)
write
1–110
Command write (code only)
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