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參數(shù)資料
| 型號： | S1D13700F02A100 |
| 元件分類： | 顯示控制器 |
| 英文描述： | 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64 |
| 封裝： | LEAD FREE, TQFP-64 |
| 文件頁數(shù)： | 15/108頁 |
| 文件大小： | 1373K |
| 代理商： | S1D13700F02A100 |
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2: PINS
S1D13700 Technical Manual
EPSON
9
2.2
Pin Functions
2.2.1
Power Supply Pins
Note 1: Because the spike power supply current in the S1D13700 could reach levels that are several
tens higher than the average amount of dynamically consumed current, measures must be
taken to minimize the power supply impedance of the S1D13700. For example, use thick
power supply wiring from the power supply to the S1D13700 or insert a capacitor of 0.47 mF or
more (with good frequency characteristics) between VDD and VSS close to the S1D13700.
These measures will help to reduce power supply impedance.
2.2.2
Oscillator and Clock Input Pins
Note 2: Because the external clock fed in from the CLKI pin is needed to internally generate the
fundamental timing in the S1D13700, the oscillation characteristic requirements given in
Pin Name
Function
HIOVDD
Power supply for host interface I/O drive. Connect a 5 V or 3.3 V power supply to this pin. (Shared
with MPU power supply pin, VCC)
Note 1
NIOVDD
Power supply for LCD I/O drive other than host of interface I/O. Connect a 5 V or 3.3 V power supply
to this pin.
Note 1
COREVDD
Power supply for internal logic. Connect a 3.3 V power supply to this pin.
Note 1
VSS
Connects to 0 V earth ground (GND).
CLKI
Generally used as the input clock source for the bus and memory clocks.
XCG1
XCD1
These pins are used to connect a crystal resonator for the internal clock-generating oscillator. For
details, see Section 4.2 “Oscillator Circuit” on page 70. To use the external clock (fed in from the
CLKI pin), x XCG1 for input with a pullup resistor and leave XCD1 open.
Note 2
CNF0
CNF1
Input, active low
Set the frequency divide ratio of the display clock (pixel clock) relative to CLKI or an internally gener-
ated system clock.
CNF3
CNF2
Clock Retio
0
1/4
0
1
1/8
1
0
1/16
1
Not USE
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