參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 85/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
10
EPSON
S1C88848 TECHNICAL MANUAL
3 CPU AND MEMORY CONFIGURATION
3.3 Exception Processing Vectors
Address 000000H to address 000029H in the
program area of the S1C88848 is assigned as
exception processing vectors. Furthermore, from
address 00002CH to address 0000FFH, software
interrupt vectors are assignable to any two bytes
which begin with an even address.
Table 3.3.1 lists the vector addresses and the
exception processing factors to which they
correspond.
Table 3.3.1 Vector addresses and
exception processing factors
Vector
address
000000H
000002H
000004H
000006H
000008H
00000AH
00000CH
00000EH
000010H
000012H
000014H
000016H
000018H
00001AH
00001CH
00001EH
000020H
000022H
000024H
000026H
000028H
00002AH
00002CH
:
0000FEH
Priority
High
↑
↓
Low
No
priority
rating
Exception processing factor
Reset
Zero division
Watchdog timer (NMI)
Programmable timer 1 interrupt
Programmable timer 0 interrupt
K10, K11 input interrupt
K04–K07 input interrupt
K00–K03 input interrupt
Serial I/F error interrupt
Serial I/F receiving complete interrupt
Serial I/F transmitting complete interrupt
Stopwatch timer 100 Hz interrupt
Stopwatch timer 10 Hz interrupt
Stopwatch timer 1 Hz interrupt
Clock timer 32 Hz interrupt
Clock timer 8 Hz interrupt
Clock timer 2 Hz interrupt
Clock timer 1 Hz interrupt
Remote-control carrier output interrupt
Programmable timer 3 interrupt
Programmable timer 2 interrupt
System reserved (cannot be used)
Software interrupt
For each vector address and the address after it, the
start address of the exception processing routine is
written into the subordinate and super ordinate
sequence. When an exception processing factor is
generated, the exception processing routine is
executed starting from the recorded address.
When multiple exception processing factors are
generated at the same time, execution starts with
the highest priority item.
The priority sequence shown in Table 3.3.1 assumes
that the interrupt priority levels are all the same.
The interrupt priority levels can be set by software
in each system. (See Section 5.15 "Interrupt and
Standby Status".)
Note: For exception processing other than reset,
SC (system condition flag) and PC (program
counter) are evacuated to the stack and
branches to the exception processing
routines. Consequently, when returning to
the main routine from exception processing
routines, please use the RETE instruction.
See the "S1C88 Core CPU Manual" for information
on CPU operations when an exception processing
factor is generated.
3.4 CC (Customized Condition Flag)
The S1C88848 does not use the customized condi-
tion flag (CC) in the core CPU. Accordingly, it
cannot be used as a branching condition for the
conditional branching instruction (JRS, CARS).
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