參數(shù)資料
型號(hào)： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁(yè)數(shù)： 167/174頁(yè)
文件大小： 1304K
代理商： S1C88848D0A0100
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84
EPSON
S1C88848 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
When "0" is written to FCSELx, the noise rejector is
not selected and the counting is done directly by an
external clock input to the K10 (K11) input port
terminal.
At initial reset, FCSELx is set to "0".
PLPOL0: 00FF31HD5
PLPOL2: 00FF39HD5
Select the pulse polarity for the K10 and K11 input
port terminals.
In event counter mode
When "1" is written: Rising edge
When "0" is written: Falling edge
Reading:
Valid
In the event counter mode, PLPOLx is used to
select whether the falling edge of the external clock,
which is input to the K10 (EVIN0) input port
terminal for timer 0 or the K11 (EVIN2) input port
terminal for timer 2, is counted or the rising edge is
counted. When "0" is written to PLPOLx, the falling
edge is selected and when "1" is written, the rising
edge is selected.
In pulse width measurement mode
When "1" is written: High level pulse width
measurement
When "0" is written: LOW level pulse width
measurement
Reading:
Valid
In the pulse width measurement mode, PLPOLx is
used to select whether the LOW level width of the
external signal, which is input to the K10 (EVIN0)
input port terminal for timer 0 or the K11 (EVIN2)
input port terminal for timer 2, is measured or the
HIGH level is measured. When "0" is written to
PLPOLx, the LOW level width measurement is
selected and when "1" is written, the HIGH level
width measurement is selected.
In the normal mode (EVCNTx = FCSELx = "0"), the
setting of PLPOLx becomes invalid.
At initial reset, PLPOLx is set to "0".
CONT0: 00FF31HD2
CONT1: 00FF32HD2
CONT2: 00FF39HD2
CONT3: 00FF3AHD2
Selects the continuous/one-shot mode.
When "1" is written: Continuous mode
When "0" is written: One-shot mode
Reading:
Valid
CONTx is used to select whether timer x will be
used in the continuous mode or in the one-shot
mode.
By writing "1" to CONTx, the programmable timer
is set to the continuous mode. In the continuous
mode, the initial counter value is automatically
loaded when an underflow is generated, and
counting is continued. On the other hand, when
writing "0" to CONTx, the programmable timer is
set to the one-shot mode. The counter loads an
initial value and stops when an underflow is
generated. At this time, PRUNx is automatically
reset to "0".
At initial reset, this register is set to "0" (one-shot
mode).
RLD00–RLD07: 00FF33H
RLD10–RLD17: 00FF34H
RLD20–RLD27: 00FF3BH
RLD30–RLD37: 00FF3CH
Sets the initial value for the counter.
The reload data set in RLDx is loaded into the
counter of timer x and is counted down with that as
the initial value.
Reload data is loaded to the counter under two
conditions, when "1" is written to PSETx and when
the counter underflow automatically loads.
At initial reset, this register is set to "FFH".
PTD00–PTD07: 00FF35H
PTD10–PTD17: 00FF36H
PTD20–PTD27: 00FF3DH
PTD30–PTD37: 00FF3EH
Timer x data is read from PTDx.
These bits act as a buffer to maintain the counter
data during readout, and the data can be read as
optional timing. However, in the 16-bit mode, to
avoid a read error (data error when a borrow from
timer 0 (timer 2) to timer 1 (timer 3) is generated in
the middle of reading PTD0 and PTD1 (PTD2 and
PTD3)), PTD1 (PTD3) latches the timer 1 (timer 3)
counter data according to the reading of PTD0
(PTD2).
The latched status of PTD1 (PTD3) is canceled
according to the readout of PTD1 (PTD3) or when
0.73–1.22 msec (depends on the readout timing) has
elapsed. Therefore, in 16-bit mode, be sure to read
the counter data of PTD0 (PTD2) and PTD1 (PTD3)
in order.
Since these bits are exclusively for reading, the
write operation is invalid.
At initial reset, these bits are set to "FFH".
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