參數(shù)資料
型號(hào)： S1C88848D0A0100
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁(yè)數(shù)： 33/174頁(yè)
文件大小： 1304K
代理商： S1C88848D0A0100
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120
EPSON
S1C88848 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Remote Controller)
RT0, RT1: 00FF28HD5, D6
Selects the
τ (reference cycle).
When controlling in the hard-timer mode, select the
τ (reference cycle) that is used as a reference for the
timing generation.
Table 5.13.6.3
τ (reference cycle) setting
fcarrier / 32
fcarrier / 20
fcarrier / 16
fcarrier / 12
RT1
1
0
RT0
1
0
1
0
τ dividing ratio
fcarrier indicates the carrier frequency selected
with RCDIV.
This setting must be done when the remote
controller is in OFF status (REMC = "0").
At initial reset, RT is set to "0" (fcarrier/12).
ROUT0, ROUT1: 00FF2AHD6, D7
When controlling in the hard-timer mode, select the
carrier output width.
Table 5.13.6.4 Setting of carrier output width
3
τ
2
τ
1
τ
0
τ
ROUT1
1
0
ROUT0
1
0
1
0
Carrier output width
By writing data to this register, the carrier for set
τ
cycles is output from the REM (R26) terminal in
synchronization with the rising edge of the
τ
waveform immediately after that.
The setting (writing) of carrier output width must
be done at every bit of the transmission data.
At initial reset and when REMC is set to "0", ROUT
is set to "0" (0
τ).
Note: The ROUT register is for the exclusive use
of the hard-timer mode. When controlling
with the soft-timer mode, be sure not to write
data to this register to prevent malfunction.
RIC0–RIC3: 00FF29HD4–D7
The
τ cycle count for generating a REM interrupt is
set to this register.
By writing data to this register when the REM
circuit has been ON (REMC = "1"), the counting of
τ
waveform is started by synchronizing with the
rising edge of the
τ waveform immediately after
that. When the count becomes the number set in
this register, an interrupt occurs. Set the next
transmission data and interrupt timing using this
interrupt.
Do not set "0FH" in this register.
The setting (writing) of interrupt
τ cycle must be
done at every bit of the transmission data.
RIC is exclusively for writing, it always becomes "0"
during reading.
At initial reset, RIC is undefined.
Note: The RIC register is for the exclusive use of
the hard-timer mode. When controlling with
the soft-timer mode, be sure not to write
data to this register to prevent malfunction.
PREM0, PREM1: 00FF21HD6, D7
Sets the REM interrupt priority level. The two bits
PREM0 and PREM1 are the interrupt priority
registers corresponding to the REM interrupt.
Table 5.13.6.5 shows the interrupt priority level
which can be set by this register.
Table 5.13.6.5 Interrupt priority level settings
PREM1
PREM0
Interrupt priority level
1
0
1
0
1
0
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
At initial reset, PREM is set to "0" (level 0).
EREM: 00FF26HD5
Enables or disables the generation of an interrupt
for the CPU.
When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
Reading:
Valid
EREM is the interrupt enable register that
corresponds to the REM interrupt factor. The REM
interrupt is enabled when this register is set to "1"
and is disabled when this register is set to "0".
At initial reset, EREM is set to "0" (interrupt
disabled).
FREM: 00FF27HD5
Indicates the REM interrupt generation status.
When "1" is read:
Interrupt factor present
When "0" is read:
Interrupt factor not present
When "1" is written: Resets factor flag
When "0" is written: Invalid
FREM is the interrupt factor flag that corresponds
to the REM interrupt and is set to "1" when the
interrupt
τ cycle set with the RIC register has
passed (counting of the
τ waveform has
completed).
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