參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 166/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
S1C88848 TECHNICAL MANUAL
EPSON
83
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
MODE160: 00FF30HD4
MODE162: 00FF38HD4
Selects the 8/16-bit mode.
When "1" is written: 16 bits
× 1 channel
When "0" is written: 8 bits
× 2 channels
Reading:
Valid
MODE160 is used to select whether timers 0 and 1
will be used as 2 channel independent 8-bit timers
or as a 1 channel combined 16-bit timer. The 8/16-
bit mode for timers 2 and 3 is selected with
MODE162. When "0" is written to MODE16x, 8-bit
× 2 channels is selected and when "1" is written, 16-
bit
× 1 channel is selected.
At initial reset, MODE16x is set to "0" (8-bit
× 2
channels).
CKSEL0: 00FF30HD0
CKSEL1: 00FF30HD1
CKSEL2: 00FF38HD0
CKSEL3: 00FF38HD1
Selects the source clock of the prescaler.
When "1" is written: OSC3 clock
When "0" is written: OSC1 clock
Reading:
Valid
CKSELx is used to select the source clock of
prescaler x (for timer x) from OSC1 and OSC3.
When "0" is written to CKSELx, OSC1 is selected
and when "1" is written, OSC3 is selected.
When event counter mode has been selected, the
setting of the CKSEL0 or CKSEL2 becomes invalid.
In the same way, setting of the CKSEL1 or CKSEL3
becomes invalid when 16-bit mode has been
selected.
At initial reset, this register is set to "0" (OSC1
clock).
PSC00, PSC01: 00FF31HD3, D4
PSC10, PSC11: 00FF32HD3, D4
PSC20, PSC21: 00FF39HD3, D4
PSC30, PSC31: 00FF3AHD3, D4
Select the dividing ratio of the prescaler.
Two-bit PSCx0 and PSCx1 is the prescaler dividing
ratio selection registers for timer x. The prescaler
dividing ratios that can be set by these registers are
shown in Table 5.10.10.2.
Table 5.10.10.2 Selection of prescaler dividing ratio
PSC31
PSC21
PSC11
PSC01
PSC30
PSC20
PSC10
PSC00
Prescaler dividing ratio
1
0
1
0
1
0
Source clock / 64
Source clock / 16
Source clock / 4
Source clock / 1
When event counter mode has been selected, the
setting of the PSC0 or PSC2 becomes invalid. In the
same way, the setting of the PSC1 or PSC3 becomes
invalid when 16-bit mode has been selected.
At initial reset, this register is set to "0" (input
clock/1).
EVCNT0: 00FF31HD7
EVCNT2: 00FF39HD7
Select the counter mode for the timer 0 and timer 2.
When "1" is written: Event counter mode
When "0" is written: Timer mode
Reading:
Valid
EVCNTx is used to select whether timer x will be
used as an event counter or a timer. When "1" is
written to EVCNTx, the event counter mode is
selected and when "0" is written, the timer mode is
selected.
At initial reset, EVCNTx is set to "0" (timer mode).
FCSEL0: 00FF31HD6
FCSEL2: 00FF39HD6
Select the function for each counter mode of timer 0
and timer 2.
In timer mode
When "1" is written: Pulse width measurement
timer mode
When "0" is written: Normal mode
Reading:
Valid
In the timer mode, select whether timer 0 or timer 2
will be used as a pulse width measurement timer or
a normal timer. When "1" is written to FCSELx,
timer x is set in the pulse width measurement mode
and the counting is done according to the signal
level input to the K10 (EVIN0) input port terminal
for timer 0 or the K11 (EVIN2) input port terminal
for timer 2. When "0" is written to FCSELx, the
normal mode is selected and the counting is not
affected by the input port terminal.
In event counter mode
When "1" is written: With noise rejecter
When "0" is written: Without noise rejecter
Reading:
Valid
In the event counter mode, FCSELx is used to select
whether the noise rejecter for the K10 (EVIN0)
input port terminal for timer 0 or the K11 (EVIN2)
input port terminal for timer 2 is enabled or not.
When "1" is written to FCSELx, the noise rejecter is
selected and counting is done by an external clock
with 0.98 msec or more pulse width. The noise
rejecter allows clocking counter at the second
falling edge of the internal 2,048 Hz signal after
changing the input level of the K10 (K11) input port
terminal. Consequently, the pulse width that can
reliably be rejected is 0.48 msec.
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