參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 168/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
S1C88848 TECHNICAL MANUAL
EPSON
85
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
PSET0: 00FF31HD1
PSET1: 00FF32HD1
PSET2: 00FF39HD1
PSET3: 00FF3AHD1
Presets the reload data to the counter.
When "1" is written: Preset
When "0" is written: No operation
Reading:
Always "0"
By writing "1" to PSETx, the reload data in PLDx is
preset to the counter of timer x. When the counter
of timer x is preset in the RUN status, it restarts
immediately after presetting.
In the case of STOP status, the reload data that has
been preset is maintained.
No operation results when "0" is written.
When the 16-bit mode is selected, writing "1" to
PSET1 or PSET3 is invalid.
This bit is exclusively for writing, it always be-
comes "0" during reading.
PRUN0: 00FF31HD0
PRUN1: 00FF32HD0
PRUN2: 00FF39HD0
PRUN3: 00FF3AHD0
Controls the RUN/STOP of the counter.
When "1" is written: RUN
When "0" is written: STOP
Reading:
Valid
The counter of timer x starts down-counting by
writing "1" to PRUNx and stops by writing "0".
In the STOP status, the counter data is maintained
until it is preset or set in the next RUN status. Also,
when the STOP status changes to the RUN status,
the data that was maintained can be used for
resuming the count.
When the 16-bit mode is selected, PRUN1 or
PRUN3 is fixed at "0".
At initial reset and when an underflow is generated
in the one-shot mode, this register is set to "0"
(STOP).
CHSEL: 00FF30HD3
Selects a channel for generating the TOUT signal.
When "1" is written: Timer 1 underflow
When "0" is written: Timer 0 underflow
Reading:
Valid
Select whether the timer 0 underflow will be used
for the TOUT signal or the timer 1 underflow will
be used. When "0" is written to CHSEL, timer 0 is
selected and when "1" is written, timer 1 is
selected.When the 16-bit mode has been selected, it
is fixed to timer 1 (underflow of the 16-bit timer),
and setting of CHSEL becomes invalid.
At initial reset, CHSEL is set to "0" (timer 0
underflow).
PTOUT: 00FF30HD2
Controls the TOUT (programmable timer output
clock) signal output.
When "1" is written: TOUT signal output ON
When "0" is written: TOUT signal output OFF
Reading:
Valid
PTOUT is the output control register for TOUT
_________
(TOUT) signal. When "1" is set to the register, the
_________
TOUT (TOUT) signal is output from the output
port terminal R27 (R26). When "0" is set, the R27
goes HIGH (VDD) and the R26 goes LOW (VSS).
To output the TOUT signal, "1" must always be set
for the data register R27D. The data register R26D
_________
does not affect the TOUT output.
At initial reset, PTOUT is set to "0" (OFF).
_________
The TOUT signal can be output from R26 only
when the function is selected by mask option.
PPT0, PPT1: 00FF21HD2, D3
PPT2, PPT3: 00FF21HD4, D5
Set the priority level of the programmable timer
interrupt.
PPT0–PPT1 and PPT2–PPT3 are the interrupt
priority registers that correspond to the timers 0–1
and timers 2–3 interrupts, respectively. Table
5.10.10.3 shows the interrupt priority level which
can be set by this register.
Table 5.10.10.3 Interrupt priority level settings
PPT3
PPT1
PPT2
PPT0
Interrupt priority level
1
0
1
0
1
0
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
At initial reset, this register is set to "0" (level 0).
EPT0: 00FF23HD6
EPT1: 00FF23HD7
EPT2: 00FF26HD6
EPT3: 00FF26HD7
Enables or disables the generation of an interrupt
for the CPU.
When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
Reading:
Valid
EPTx is the interrupt enable register that
corresponds to the interrupt factor for timer x.
Interrupts set to "1" are enabled and interrupts set
to "0" are disabled.
When the 16-bit mode is selected, setting of EPT0 or
EPT2 becomes invalid.
At initial reset, this register is set to "0" (interrupt
disabled).
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