參數(shù)資料
型號(hào)： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁(yè)數(shù)： 28/174頁(yè)
文件大小： 1304K
代理商： S1C88848D0A0100
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S1C88848 TECHNICAL MANUAL
EPSON
115
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Remote Controller)
The actual time of
τ (reference cycle) can be found
using the following expression according to the
OSC3 oscillation frequency, carrier cycle selection
and the above selection.
τ (reference cycle) [sec] = 1 / (fOSC3 × DIV1 × DIV2)
fOSC3:OSC3 oscillation frequency
DIV1: Content of carrier cycle (dividing ratio) set
with RCDIV (1/64 or 1/96)
DIV2: Content of
τ dividing ratio set with RT1 and
RT0 (1/12, 1/16, 1/20 or 1/32)
Table 5.13.5.2 shows the examples of
τ (reference
cycle) when fOSC3 is 3.64 MHz.
Table 5.13.5.2
τ (reference cycle) examples
RCDIV
1
0
Register settings
RT1
1
0
1
0
fOSC3 = 3.64 MHz
0.844 msec (1184.9 Hz)
0.527 msec (1895.8 Hz)
0.422 msec (2369.8 Hz)
0.316 msec (3159.7 Hz)
0.563 msec (1777.3 Hz)
0.352 msec (2843.8 Hz)
0.281 msec (3554.7 Hz)
0.211 msec (4739.6 Hz)
RT0
1
0
1
0
1
0
1
0
τ (reference cycle)
The carrier output ON time can be set to 4 types (0
τ
to 3
τ) based on the τ (reference cycle) set, so set the
τ (reference cycle) after due consideration.
Figure 5.13.5.1 shows the
τ waveform when fcarrier
/12 has been selected.
τ waveform is kept on outputting from the τ
(reference cycle) generation circuit according to the
set dividing ratio while REMC is "1".
Carrier
τ waveform
τ
Fig. 5.13.5.1
τ waveform (when fcarrier /12 is selected)
It is possible to set
τ (reference cycle) even if the
OSC3 oscillation circuit is in OFF status.
Furthermore, when it is set once, the set contents
are maintained until an initial reset is performed.
When REMC is set to "0", the REM circuit stops
synchronously with
τ. This timing is shown in
Figure 5.13.5.2.
Stop synchronously with
τ
REMC
Carrier
τ waveform
Fig. 5.13.5.2 REM circuit stop timing
Maximum of 384 machine cycles* are required until
the REM circuit stops after REMC is set to "0". Even
if the CPU clock is changed from OSC3 to OSC1
after REMC is set to "0", OSC3 must not be turned
OFF before the REM circuit stops.
This time depends on the value of the set τ cycle.
If a shorter
τ cycle is set, the maximum time
required for the REM circuit to stop after REMC
is set to "0" is shortened.
If the REM circuit is restarted from OFF state with
REMC = "0", the timing of the
τ waveform rises one
carrier before the set division ratio.
REMC
Carrier
τ waveform
Fig. 5.13.5.3
τ generation circuit restart timing
Note: The setting of the RT register should be
done when the REM circuit is OFF (REMC =
"0") before starting remote transmission.
Changing the contents when the REM circuit
is ON may cause a malfunction.
■ Setting of carrier output width
In the soft-timer mode, the carrier output width
(carrier output ON time) is controlled by writing to
REMSO, but in the hard-timer mode, it can be
specified with values 0 to 3, which mean the
number of
τ cycles described above, in each
transmission data bit. Since the carrier output ON/
OFF is controlled by the hardware in synchronizing
with
τ waveform, it is unnecessary to watch the ON
time and to specify the OFF timing by the software.
The carrier output width can be selected by writing
data to the REM output ON time setting register
ROUT1 and ROUT0 from among 4 types as shown
in Table 5.13.5.3.
Table 5.13.5.3 Setting of carrier output width
3
τ
2
τ
1
τ
0
τ
ROUT1
1
0
ROUT0
1
0
1
0
Carrier output width
The carrier is output in synchronizing with the
rising edge of the
τ waveform after writing data to
ROUT. Data written to ROUT is maintained while
the REM circuit is ON until the next data is written.
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