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7 DETAILS OF INSTRUCTIONS
S1C17 FAMILY S1C17 CORE MANUAL
EPSON
7-77
ld.b %rd, [%rb]
ld.b %rd, [%rb]+
ld.b %rd, [%rb]-
ld.b %rd, -[%rb]
Function
Signed byte data transfer
ld.b %rd, [%rb]
Standard)
rd
(7:0)
← B[rb], rd(15:8) ← B[rb](7), rd(23:16) ← 0
Extension 1) rd(7:0)
← B[rb + imm13], rd(15:8) ← B[rb + imm13](7), rd(24:16) ← 0
Extension 2) rd(7:0)
← B[rb + imm24], rd(15:8) ← B[rb + imm24](7), rd(24:16) ← 0
ld.b %rd, [%rb]+ (with post-increment option)
Standard)
rd
(7:0)
← B[rb], rd(15:8) ← B[rb](7), rd(23:16) ← 0, rb(23:0) ← rb(23:0) + 1
Extension 1) rd(7:0)
← B[rb + imm13], rd(15:8) ← B[rb + imm13](7), rd(24:16) ← 0,
rb
(23:0)
← rb(23:0) + imm13
Extension 2) rd(7:0)
← B[rb + imm24], rd(15:8) ← B[rb + imm24](7), rd(24:16) ← 0,
rb
(23:0)
← rb(23:0) + imm24
ld.b %rd, [%rb]- (with post-decrement option)
Standard)
rd
(7:0)
← B[rb], rd(15:8) ← B[rb](7), rd(23:16) ← 0, rb(23:0) ← rb(23:0) - 1
Extension 1) rd(7:0)
← B[rb + imm13], rd(15:8) ← B[rb + imm13](7), rd(24:16) ← 0,
rb
(23:0)
← rb(23:0) - imm13
Extension 2) rd(7:0)
← B[rb + imm24], rd(15:8) ← B[rb + imm24](7), rd(24:16) ← 0,
rb
(23:0)
← rb(23:0) - imm24
ld.b %rd, -[%rb] (with pre-decrement option)
Standard)
rb
(23:0)
← rb(23:0) - 1, rd(7:0) ← B[rb], rd(15:8) ← B[rb](7), rd(23:16) ← 0
Extension 1) rb(23:0)
← rb(23:0) - imm13, rd(7:0) ← B[rb + imm13],
rd
(15:8)
← B[rb + imm13](7), rd(24:16) ← 0
Extension 2) rb(23:0)
← rb(23:0) - imm24, rd(7:0) ← B[rb + imm24],
rd
(15:8)
← B[rb + imm24](7), rd(24:16) ← 0
Code
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0 0 1 0 0 0
r d
0 0 0 0
r b
ld.b
%rd,[%rb]
|
0 0 1 0 0 0
r d
0 1 0 0
r b
ld.b
%rd,[%rb]+
|
0 0 1 0 0 0
r d
1 1 0 0
r b
ld.b
%rd,[%rb]-
|
0 0 1 0 0 0
r d
1 0 0 0
r b
ld.b
%rd,-[%rb]
|
Flag
IL IE
C
V
Z
N
– – – – – –
|
Mode
Src:Register indirect %rb = %r0 to %r7
Dst:Register direct %rd = %r0 to %r7
CLK
One cycle (two cycles when the ext instruction or an increment/decrement option is used)
Description (1) Standard
ld.b
%rd,[%rb]
; memory address = rb
The byte data in the specified memory location is transferred to the rd register after being sign-
extended to 16 bits. The rb register contains the memory address to be accessed. The eight high-
order bits of the rd register are set to 0.