7 DETAILS OF INSTRUCTIONS
7-54
EPSON
S1C17 FAMILY S1C17 CORE MANUAL
ld [%rb], %rs
ld [%rb]+, %rs
ld [%rb]-, %rs
ld -[%rb], %rs
Function
16-bit data transfer
ld [%rb], %rs
Standard)
W[rb]
← rs(15:0)
Extension 1) W[rb + imm13]
← rs(15:0)
Extension 2) W[rb + imm24]
← rs(15:0)
ld [%rb]+, %rs (with post-increment option)
Standard)
W[rb]
← rs(15:0), rb(23:0) ← rb(23:0) + 2
Extension 1) W[rb + imm13]
← rs(15:0), rb(23:0) ← rb(23:0) + imm13
Extension 2) W[rb + imm24]
← rs(15:0), rb(23:0) ← rb(23:0) + imm24
ld [%rb]-, %rs (with post-decrement option)
Standard)
W[rb]
← rs(15:0), rb(23:0) ← rb(23:0) - 2
Extension 1) W[rb + imm13]
← rs(15:0), rb(23:0) ← rb(23:0) - imm13
Extension 2) W[rb + imm24]
← rs(15:0), rb(23:0) ← rb(23:0) - imm24
ld -[%rb], %rs (with pre-decrement option)
Standard)
rb
(23:0)
← rb(23:0) - 2, W[rb] ← rs(15:0)
Extension 1) rb(23:0)
← rb(23:0) - imm13, W[rb + imm13] ← rs(15:0)
Extension 2) rb(23:0)
← rb(23:0) - imm24, W[rb + imm24] ← rs(15:0)
Code
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0 0 1 0 0 1
r s
0 0 1 0
r b
ld
[%rb],%rs
|
0 0 1 0 0 1
r s
0 1 1 0
r b
ld
[%rb]+,%rs
|
0 0 1 0 0 1
r s
1 1 1 0
r b
ld
[%rb]-,%rs
|
0 0 1 0 0 1
r s
1 0 1 0
r b
ld
-[%rb],%rs
|
Flag
IL IE
C
V
Z
N
– – – – – –
|
Mode
Src:Register direct %rs = %r0 to %r7
Dst:Register indirect %rb = %r0 to %r7
CLK
One cycle (two cycles when the ext instruction or an increment/decrement option is used)
Description (1) Standard
ld
[%rb],%rs
; memory address = rb
The 16 low-order bits of the rs register are transferred to the specified memory location. The rb
register contains the memory address to be accessed.
(2) Extension 1
ext
imm13
ld
[%rb],%rs
; memory address = rb + imm13
The ext instruction changes the addressing mode to register indirect addressing with
displacement. As a result, the 16 low-order bits of the rs register are transferred to the address
indicated by the content of the rb register with the 13-bit immediate imm13 added. The content
of the rb register is not altered.