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參數(shù)資料
| 型號(hào)： | S1C7XXXF00E199 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 90 MHz, RISC MICROCONTROLLER, PQFP |
| 文件頁(yè)數(shù)： | 123/196頁(yè) |
| 文件大?。?/td> | 1650K |
| 代理商： | S1C7XXXF00E199 |
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5 INSTRUCTION SET
5-6
EPSON
S1C17 FAMILY S1C17 CORE MANUAL
5.2.3 Register Indirect Addressing
In this mode, memory is accessed indirectly by specifying a general-purpose register or the stack pointer that holds
the address needed. This addressing mode is used only for load instructions that have [%rb] or [%sp] as the op-
erand. Actually, this general-purpose register is written as [%r0], [%r1], ... [%r7], or [%sp], with the register
name enclosed in brackets “[].”
The processor refers to the content of a specified register as the base address, and transfers data in the format that is
determined by the type of load instruction.
Examples: Memory
→ Register
ld.b
%r0,[%r1]
; Load 8-bit data
ld
%r0,[%r1]
; Load 16-bit data
ld.a
%r0,[%r1]
; Load 24-bit data
Register
→ Memory
ld.b
[%r1],%r0
; Store 8-bit data
ld
[%r1],%r0
; Store 16-bit data
ld.a
[%r1],%r0
; Store 24-bit data
In this example, the address indicated by r1 is the memory address from or to which data is to be trans-
ferred.
In 16-bit and 24-bit transfers, the base address that is set in a register must be on a 16-bit boundary (least significant
address bit = 0) or 32-bit boundary (2 low-order address bits = 0), respectively. Otherwise, an address-misaligned
interrupt will be generated.
5.2.4 Register Indirect Addressing with Post-increment/decrement or
Pre-decrement
As in register indirect addressing, the memory location to be accessed is specified indirectly by a general-purpose
register or the stack pointer. In this addressing mode, the base address held in a specified register is incremented/
decremented by an amount equal to the transferred data size before or after a data transfer. In this way, data can be
read from or written to continuous addresses in memory only by setting the start address once at the beginning.
Increment/decrement size (without ext)
Byte transfer (ld.b, ld.ub): rb
→ rb + 1, rb → rb - 1
16-bit transfer (ld):
rb
→ rb + 2, rb → rb - 2
24-bit transfer (ld.a):
rb
→ rb + 4, rb → rb - 4
Register indirect addressing with post-increment
When a data transfer finishes, the base address is incremented.
This addressing mode is specified by enclosing the register name in brackets “[],” which is then suffixed by “+.”
The register name is actually written as [%r0]+, [%r1]+, ... [%r7]+, or [%sp]+.
Register indirect addressing with post-decrement
When a data transfer finishes, the base address is decremented.
This addressing mode is specified by enclosing the register name in brackets “[],” which is then suffixed by “-.”
The register name is actually written as [%r0]-, [%r1]-, ... [%r7]-, or [%sp]-.
Register indirect addressing with pre-decrement
The base address is decremented before a data transfer starts.
This addressing mode is specified by enclosing the register name in brackets “[],” which is prefixed by “-.”
The register name is actually written as -[%r0], -[%r1], ... -[%r7], or -[%sp].
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