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7 DETAILS OF INSTRUCTIONS
7-16
EPSON
S1C17 FAMILY S1C17 CORE MANUAL
calla
imm7
calla.d imm7
Function
PC absolute subroutine call
Standard)
sp
← sp - 4, A[sp] ← pc + 2, pc ← imm7
Extension 1) sp
← sp - 4, A[sp] ← pc + 2, pc ← imm20
Extension 2) sp
← sp - 4, A[sp] ← pc + 2, pc ← imm24
Code
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 1 0 1 0
imm7
calla
|
0 0 0 0 0 1 0 1 1
imm7
calla.d
|
Flag
IL IE
C
V
Z
N
– – – – – –
|
Mode
PC absolute
CLK
calla
Four cycles
calla.d
Three cycles
Description (1) Standard
calla
imm7
Stores the address of the following instruction into the stack, then sets the 7-bit immediate
imm7
to the PC for calling the subroutine that starts from the address set to the PC. The LSB
of the imm7 is invalid and is always handled as 0. When the ret instruction is executed in the
subroutine, the program flow returns to the instruction following the calla instruction.
(2) Extension 1
ext
imm13
; = imm20(19:7)
call
imm7
; = "call imm20", imm7 = imm20(6:0)
The ext instruction extends the destination address into 20 bits using its 13-bit immediate
imm13
. The 20-bit destination address is set to the PC.
(3) Extension 2
ext
imm13
; imm13(3:0) = imm24(23:20)
ext
imm13
; = imm24(19:7)
call
imm7
; = "call imm24", imm7 = imm24(6:0)
The 24-bit destination address is set to the PC.
(4) Delayed branch (d bit (bit 7) = 1)
calla.d
imm7
When calla.d is specified, the d bit (bit 7) in the instruction code is set and the following
instruction becomes a delayed slot instruction. The delayed slot instruction is executed before
branching to the subroutine. Therefore the address (PC + 4) of the instruction that follows the
delayed slot instruction is stored into the stack as the return address.
When the calla.d instruction is executed, interrupts cannot occur because traps are masked
between the calla.d and delayed slot instructions.
Example
ext
0x1fff
calla
0x0
; Calls the subroutine that starts from
; address 0xfff80.
Caution
When the calla.d instruction (delayed branch) is used, be careful to ensure that the next
instruction is limited to those that can be used as a delayed slot instruction. If any other instruction
is executed, the program may operate indeterminately. For the usable instructions, refer to the
instruction list in the Appendix.