參數(shù)資料
型號(hào)： PXAC37
廠商： NXP Semiconductors N.V.
英文描述： XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce
中文描述： 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個(gè)SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce
文件頁(yè)數(shù)： 58/68頁(yè)
文件大?。?/td> 368K
代理商： PXAC37
Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
51
MERIF
Message Error Interrupt Flag (cleared by writing
‘1’)
Rx Buffer Full Interrupt Flag (cleared by writing
‘1’)
Transmit Message Complete Interrupt Flag
(should be cleared using the 2–step process
described in the section entitled Rx and Tx
Message Complete Interruptson page 47).
Receive Message Complete Interrupt Flag
(should be cleared using the 2–step process
described in the section entitled Rx and Tx
Message Complete Interruptson page 47
RBFIF
TMCIF
RMCIF
FESTR (Frame Error Status Register)
Address: MMR base + 22Ch
Access: Read, byte or word
Reset Value: 00h
FESTR
7
–
6
–
5
4
3
2
1
0
PBO
ARBLST
BERR
BOFF
ERRW
ERRP
PBO
Frame Error sub–type is Pre–Buffer Overflow
(cleared by writing ‘1’)
Frame Error sub–type is Arbitration Lost
(cleared by reading the ALCR register)
Frame Error sub–type is Bus Error (cleared by
reading the ECCR register)
Frame Error sub–type is Bus Off (cleared by
writing ‘1’)
Frame Error sub–type is Error Warning (cleared
by writing ‘1’)
Frame Error sub–type is Error Passive (cleared
by writing ‘1’)
ARBLST
BERR
BOFF
ERRW
ERRP
FEENR (Frame Error Enable Register)
Address: MMR base + 22Eh
Access: Read, byte or word
Reset Value: 00h
FEENR
7
–
6
–
5
4
3
2
1
0
PBOE
ARBLSTE
BERRE
BOFFE
ERRWE
ERRPE
PBOE
Pre–Buffer Overflow Enable (0 = disabled, 1 =
enabled)
Arbitration Lost Enable (0 = disabled, 1 =
enabled)
Bus Error Enable (0 = disabled, 1 = enabled)
Bus Off Enable (0 = disabled, 1 = enabled)
ARBLSTE
BERRE
BOFFE
ERRWE
Error Warning Enable (0 = disabled, 1 =
enabled)
Error Passive Enable (0 = disabled, 1 =
enabled)
ERRPE
MCIR (Message Complete Info Register)
Address: MMR base + 229h
Access: Read, byte or word
Reset Value: 00h
MCIR
7
–
6
–
5
4
3
2
1
0
1 or More
Object Number
1orMore
0 = No objects whose INT_EN bits are set
currently have a message complete condition. 1
= One or more objects whose INT_EN bits are
set currently have a message complete
condition.
These 5 bits encode the lowest object number
(0 – 31) of all objects whose INT_EN bits are
set
AND
who currently have a message
complete condition. If there are no such objects
(1orMore = 0), these bits will be 00000b.
Object Number
MEIR (Message Error Info Register)
Address: MMR base + 22Ah
Access: Read, byte or word
Reset Value: 00h
MEIR
7
TBU
6
5
4
3
2
1
0
FRAG
RBF
Object Number
[TBU FRAG RBF]
001 = Most recent is Rx Buffer Full interrupt.
010 = Most recent is Fragmentation Error
interrupt.
100 = Most recent is Tx Buffer Underflow
interrupt.
These 5 bits encode the object number (0 – 31)
of the Message Object experiencing the most
recent Message Error (Tx Buffer Underflow,
Fragmentation Error, or Rx Buffer Full)
condition. If more than one object are
encountering Message Errors, only the most
recent object number will be available.
Object Number
MCPLH (Message Complete Status Flags High)
Address: MMR base + 226h
Access: Read/Clear, byte or word
Reset Value: 0000h
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