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| 型號(hào)： | PXAC37 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| 中文描述： | 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個(gè)SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce |
| 文件頁數(shù)： | 29/68頁 |
| 文件大?。?/td> | 368K |
| 代理商： | PXAC37 |
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Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
22
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, S0ADDR, and the
address mask, S0ADEN. S0ADEN is used to define which bits in the
S0ADDR are to be used and which bits are “don’t care”. The
S0ADEN mask can be logically ANDed with the S0ADDR to create
the “Given” address which the master will use for addressing each
of the slaves. Use of the Given address allows multiple slaves to be
recognized while excluding others. The following examples will help
to show the versatility of this scheme:
Slave 0
S0ADDR =
S0ADEN =
Given =
1100 0000
1111 1101
1100 00X0
Slave 1
S0ADDR =
S0ADEN =
Given =
1100 0000
1111 1110
1100 000X
In the above example S0ADDR is the same and the S0ADEN data
is used to differentiate between the two slaves. Slave 0 requires a 0
in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Slave 0
S0ADDR =
S0ADEN =
Given =
1100 0000
1111 1001
1100 0XX0
Slave 1
S0ADDR =
S0ADEN =
Given =
1110 0000
1111 1010
1110 0X0X
Slave 2
S0ADDR =
S0ADEN =
Given =
1110 0000
1111 1100
1110 00XX
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the
logical OR of S0ADDR and S0ADEN. Zeros in this result are treated
as don’t–cares. In most cases, interpreting the don’t–cares as ones,
the broadcast address will be FF hexadecimal.
Upon Reset, S0ADDR and S0ADEN are loaded with 0s. This
produces a given address of all “don’t cares” as well as a Broadcast
address of all “don’t cares”. This effectively disables the Automatic
Addressing mode and allows the microcontroller to use standard
UART drivers which do not make use of this feature.
BIT
S0CON.5
SYMBOL
SM2_0
FUNCTION
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2_0 is set to 1, then
RI_0 will not be activated if the received 9th data bit (RB8_0) is 0. In Mode 1, if SM2_0=1 then RI_0 will not be
activated if a valid stop bit was not received. In Mode 0, SM2_0 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. The TB8_0 bit is
not double buffered. See text for details.
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, if SM2_0=0, RB8_0 is the stop bit that was
received. In Mode 0, RB8_0 is not used.
Transmit interrupt flag. Set when another byte may be written to the UART transmitter. See text for details.
Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the end of the stop bit time
in the other modes (except see SM2_0). Must be cleared by software.
S0CON.4
S0CON.3
REN_0
TB8_0
S0CON.2
RB8_0
S0CON.1
TI_0
S0CON.0
RI_0
Where SM0_0, SM1_0 specify the serial port mode, as follows:
SM0_0
0
0
1
1
SM1_0 Mode
0
1
0
1
Description
shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
f
OSC
/16
variable
f
OSC
/32
variable
0
1
2
3
SU01330
RI_0
TI_0
RB8_0
TB8_0
REN_0
SM2_0
SM1_0
SM0_0
S0CON
Address:
S0CON 420
Bit Addressable
Reset Value: 00H
LSB
MSB
Figure 16. Serial Port Control (S0CON) Register
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