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| 型號： | PXAC37 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| 中文描述： | 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce |
| 文件頁數(shù)： | 27/68頁 |
| 文件大?。?/td> | 368K |
| 代理商： | PXAC37 |
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Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
20
1. Reception is initiated in Mode 1, 2, or 3 by the incoming start bit if
REN_0 = 1.
Serial Port Control Register
The serial port control and status register is the Special Function
Register S0CON, shown in Figure 16. This register contains not only
the mode selection bits, but also the 9th data bit for transmit and
receive TB8_0 (S0CON[3]) and RB8_0 (S0CON[2]), and the serial
port interrupt bits Transmit Interrupt flag TI_0 (S0CON[1]) and
Receive Interrupt flag RI_0 (S0CON[0]) .
Transmit Interrupt Flag
In order to allow easy use of the double–buffered UART–0
transmitter feature, the TI_0 flag is set by the UART–0 hardware
under two conditions. The first condition is the completion of any
byte transmission. This occurs at the end of the stop bit in modes 1,
2, or 3, or at the end of the eighth data bit in mode 0. The second
condition is when S0BUF is written while the UART–0 transmitter is
idle.
Generally, UART transmitters generate one interrupt per byte
transmitted. However, UART–0 generates one additional interrupt
(as defined by the stated conditions for setting the TI_0 flag). This
additional interrupt does not occur if double–buffering is bypassed
as explained below. Note: If character–oriented transmission is used
(not block–transmission of characters), there could be a second
interrupt for each character transmitted, depending on the timing of
the writes to S0BUF. For this reason, it is generally better to bypass
double–buffering when UART–0 is used in character–oriented
mode. This is also true if UART–0 is polled rather than
interrupt–driven. The interrupt occurs at the end of the last byte
transmitted when the UART becomes idle. Among other things, this
allows a program to determine when a message has been
transmitted completely. The interrupt service routine should handle
this additional interrupt.
The recommended way to use transmit double–buffering in an
application program is to have the UART interrupt service routine
handle a single byte for each interrupt occurrence. Thus, the
program will not require any special considerations for
double–buffering. Transmitted bytes will then be tightly packed with
no intervening gaps. Note: Be aware that higher priority interrupts
may cause delays in servicing a transmitter interrupt, and this would
defeat double–buffering.
9-Bit Mode
Because the ninth data bit TB8_0 (S0CON[3]) is not
double–buffered, you must insure S0CON[3] contains the intended
ninth data bit whenever it is transmitted. Alternatively, to synchronize
the ninth data bit with the rest of the data stream, you could bypass
double–buffering.
Bypassing Double-Buffering
The UART transmitter may be used as if it is single–buffered. The
recommended UART transmitter interrupt service routine (ISR)
technique to bypass double–buffering first clears the TI_0 flag
(S0CON[1]) upon entry into the ISR, as in standard practice. This
clears the interrupt that activated the ISR. Secondly, the TI_0 flag is
cleared immediately following each write to S0BUF. This clears the
interrupt flag that would otherwise direct the program to write to the
second transmitter buffer. If there is any possibility that a higher
priority interrupt might become active between the write to S0BUF
and the clearing of the TI_0 flag, the interrupt system may have to
be temporarily disabled during that sequence by clearing, then
setting the EA bit (IEL[7]).
CLOCKING SCHEME AND BAUD RATE
GENERATION
Clock Rates for all UART Modes
For UART Modes 0 and 2 the UART clock rate is determined by a
fixed division of the oscillator clock. For Modes 1 and 3 the UART
clock rate is determined by the overflow rates of either T1 or T2.
Baud Rates for UART Modes 0 and 2
In UART Mode 0, the baud rate is fixed at
f
osc/16. In Mode 2,
however, it is fixed rate at
f
osc/32.
Baud Rate Calculations for UART Modes 0 and 2
Baud Rate for UART Mode 0:
Baud_Rate = fosc/16
Baud Rate for UART Mode 2:
Baud_Rate = fosc/32
Baud Rates for UART Modes 1 and 3
Table 9 shows the relationship of TCLK to pre–scalar settings for all
Timers T0, T1, and T2.
Table 9. TCLK Frequencies
Pre–scalar
Value
4
0
16
0
64
1
–
1
PT1 ; SCR[3]
PT0 ;
SCR[2]
0
1
0
1
TCLK
f
osc
/4
f
osc
/16
f
osc
/64
reserved
Thus, when Timers T0, T1, and T2 are used to establish the baud
rate for Baud Clock, the maximum speed of timers/(Baud Clock) is
f
osc/4 (since the minimum pre–scalar value N is equal to 4).
Consequently, the maximum Baud_Rate equals Timer_Rate (timer
overflow) divided by 16, i.e.,
f
osc/64.
Baud Rate Calculations for UART Modes 1 and 3
Baud Rate calculations for UART Mode 1 and 3:
Baud_Rate = Timer_Rate/16
Timer_Rate = fosc/(N x (Timer_Range – Timer_Reload_Value))
where N = the TCLK prescaler value (4, 16, or 64).
and Timer_Range = 256 for Timer 1 in Mode 2.
and Timer_Range = 65536 for Timer 1 in Mode 0 and
Timer 2 in count–up mode.
The timer reload value may be calculated as follows:
Timer_Reload_Value = Timer_Range –
(fosc/(Baud_Rate*N*16))
NOTES:
1. The maximum baud rate for UART–0 in Mode 1 or 3 is fosc/64.
2. The lowest possible baud rate (for a given oscillator frequency
and N value) may be found by using a timer reload value of 0.
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