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| 型號(hào)： | PXAC37 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| 中文描述： | 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個(gè)SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce |
| 文件頁數(shù)： | 28/68頁 |
| 文件大小： | 368K |
| 代理商： | PXAC37 |
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Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
21
3. The timer reload value may never be larger than the timer range.
4. If a timer reload value calculation gives a negative or fractional
result, the baud rate requested is not possible at the given
oscillator frequency and N value.
Using Timer 2 to Generate Baud Rates
Timer T2 is a 16–bit up/down counter. As a baud rate generator,
Timer 2 is selected as a clock source for UART–0 transmitter and/or
receiver by setting TCLK0 and/or RCLK0 in T2CON (see Table 10).
As the baud rate generator, T2 is incremented as
f
osc/N where N =
4, 16, or 64 depending on TCLK as programmed in SCR bits PT1
(SCR[3]) and PTO (SCR[2]). See Table 11).
NOTE: Pin T2EX [P1.7] acts as an additional External interrupt
“INT2
/
” whenever Timer T2 is used as a baud rate generator.
Table 10. T2CON Settings
T2CON
0x418
T2CON[5]
T2CON[4]
RCLK0
TCLK0
Table 11. Prescaler Select for Timer Clock
SCR
0x440
SCR[3]
SCR[2]
PT1
PT0
STINT0
BIT
S0STAT.3 FE0
SYMBOL
FUNCTION
Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame.
Cleared by software.
Break Detect flag is set if a character is received with all bits (including STOP bit) being logic ‘0’. Thus
it gives a “Start of Break Detect” on bit 8 for Mode 1 and bit 9 for Modes 2 and 3. The break detect
feature operates independently of the UARTs and provides the START of Break Detect status bit that
a user program may poll. Cleared by software.
Overrun Error flag is set if a new character is received in the receiver buffer while it is still full (before
the software has read the previous character from the buffer), i.e., when bit 8 of a new byte is
received while RI_0 in S0CON is still set. Cleared by software.
This flag must be set to enable any of the above status flags to generate a receive interrupt (RI_0).
The only way it can be cleared is by a software write to this register.
S0STAT.2 BR0
S0STAT.1 OE0
S0STAT.0 STINT0
SU01315
OE0
BR0
FE0
—
—
—
—
S0STAT Address: S0STAT 421
Bit Addressable
Reset Value: 00H
LSB
MSB
Figure 15. Serial Port Extended Status (S0STAT) Register
Note: See also Figure 17 regarding Framing Error flag.
UART Interrupt Scheme
There are separate interrupt vectors for UART–0 transmit and
receive functions (see Table 12 below).
Table 12. Vector Locations for UART in XA
Vector Address
00A0h – 00A3h
00A4h – 00A7h
NOTE:
The transmit and receive vectors could contain the same ISR
address to work like an 8051 interrupt scheme.
Interrupt Source
UART 0 Receiver
UART 0 Transmitter
Arbitration
10
11
Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received. The 9th
one goes into bit RB_8 (S0CON[2]). Then comes a stop bit.
UART–0 can be programmed such that when the stop bit is
received, the serial port interrupt will be activated only if RB_8 = 1.
This feature is enabled by setting bit SM2_0 (S0CON[5]). A way to
use this feature in multiprocessor systems is as follows:
When the master processor wants to transmit a block of data to one
of several slaves, it first sends out an address byte which identifies
the target slave. An address byte differs from a data byte in that the
9th bit is 1 in an address byte and 0 in a data byte. With SM2_0 = 1,
no slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can examine the
received byte and see if it is being addressed. The addressed slave
will clear its SM2_0 bit and prepare to receive the data bytes that will
be coming. The slaves that weren’t being addressed leave their
SM2_0 bits set and go on about their business, ignoring the
incoming data bytes.
SM2_0 has no effect in UART Mode 0, and in UART Mode 1 can be
used to check the validity of the stop bit although this is better done
with the Framing Error flag (FE0) {S0STAT[3]}. In a Mode 1
reception, if SM2_0 = 1, the receive interrupt will not be activated
unless a valid stop bit is received.
Error Handling, Status Flags and Break Detect
UART–0 has the four error flags as described in Figure 15.
Automatic Address Recognition
Automatic Address Recognition is a feature which allows UART–0 to
recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2_0 bit. In the 9–bit UART
Modes (Mode 2 and Mode 3) the Receive Interrupt flag (RI_0)
(S0CON[0]) will be automatically set when the received byte
contains either the “Given” address or the “Broadcast” address. The
9–bit mode requires that the 9th information bit is a 1 to indicate that
the received information is an address and not data. Automatic
address recognition is shown in Figure 16.
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| PXAC37KBA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| PXAC37KBBD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
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| PXAC37KFBD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
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