參數(shù)資料
型號： PXAC37
廠商： NXP Semiconductors N.V.
英文描述： XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce
中文描述： 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce
文件頁數(shù)： 48/68頁
文件大小： 368K
代理商： PXAC37
Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
41
MNMSKL
15
Msk12
14
13
12
11
10
9
8
7
6
5
4
3
2
–
1
–
0
–
Msk11
Msk10
Msk9
Msk8
Msk7
Msk6
Msk5
Msk4
Msk3
Msk2
Msk1
Msk0
MnCTL: Message n Control Register
Address: MMR base + n8h
Access: Read, write. Byte or word access.
Reset value: 00000xxxb (unused bits are always read as ‘0’)
MNCTL
7
–
6
–
5
–
4
3
2
1
0
OBJ_EN
INT_EN
Tx/Rx
FRAG
RTR_EN
OBJ_EN
Object Enable. Enables the Message Object for
receive or transmit. 0 = disabled, 1 = enabled.
Message–Complete Interrupt Enable. Specifies
whether or not a Tx or Rx Message–Complete
for this object will cause the object’s
Message–Complete Interrupt to be generated. 0
= disabled, 1 = enabled.
Transmit or Receive. Specifies whether this is a
transmit or receive Message Object. 0 =
transmit object, 1 = receive object.
Fragmented Message Enable. Only relevant for
receive Message Objects. Enables automatic
assembly of Fragmented Rx messages. If
disabled, messages received by this object are
assumed to be single–frame, or will be
assembled by User software. 0 = disabled, 1 =
enabled.
Note:
Masking of the CAN Identifier
field by User software, for the purpose of
Message Object grouping, is disallowed for
objects using hardware Fragmentation
assembly. However, Masking of unused bit
positions in the “screener”, such is mandatory in
all cases.
INT_EN
Tx/Rx
FRAG
RTR_EN
Enable Request To Transmit. 0 = the object is
not enabled for RTR handling, 1 = the object is
enabled for RTR handling. See section entitled
RTR Handling page 46.
Message Storage
When an incoming message frame has passed acceptance filtering,
it will be automatically stored in data memory via DMA. Each
message will be stored in its corresponding buffer area. On setup,
the User is responsible for assigning a unique buffer location for
each Message Object. This is specified in the object’s MnBLR
register. The User is also required to set up the size of each buffer in
the MnBSZ register.
The XA-C3 provides a total of 512 bytes of on–chip message buffer
RAM (XRAM) which may contain part or all of the CAN/CTL
(transmit & receive) message buffer space. See Section entitled
On-Chip Message Buffer RAM (XRAM) on page 55 for details.
Note: The following discussion concerning message buffer registers
applies to transmit message retrieval as well as receive message
storage.
MBXSR (applies to all objects)
Address: MMR base + 291h
Access: Read, write, byte or word
Reset value: FFh
MBXSR
7
6
5
4
3
2
1
0
a23 – a16 of all message buffer (and XRAM) base addresses
All 32 message buffers must reside within the same 64K memory
page. This page is specified by the contents of the MBXSR
(Message Buffer and XRAM Segment Register) register. Also, the
512 byte on–chip message buffer RAM (XRAM) is always positioned
within that same 64K page pointed to by MBXSR.
Note: The XA-C3 brings out only 20 address lines to package pins.
It can, therefore, only address 1MByte of off–chip data memory (a
maximum of sixteen 64K segments). As a result, for the XA-C3, the
four most significant bits of the MBSXR register must be set to
‘0000’ if External RAM is to be used for any portion of the message
buffer space.
MnBSZ: Message n Buffer Size Register
Address: MMR base + nCh
Access: Read–modify–write, byte or word access.
Reset value: 00000xxxb
MNBSZ
7
–
6
–
5
–
4
–
3
–
2
1
0
BSZ.2
BSZ.1
BSZ.0
The size of an object’s message buffer is specified with the 3–bit
field MnBSZ[2:0] as shown in Table 23.
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