- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370028 > PXAC37 (NXP Semiconductors N.V.) XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce PDF資料下載
參數(shù)資料
| 型號： | PXAC37 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| 中文描述： | 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce |
| 文件頁數(shù)： | 56/68頁 |
| 文件大?。?/td> | 368K |
| 代理商： | PXAC37 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁當(dāng)前第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
49
Message Error Interrupt
There are two possible sources of a Message Error Interrupt: Tx
Buffer Underflow, and Fragmentation Error. When either of these
conditions occur for any Message Object, the Message Error
Interrupt Flag (CANINTFLG[3]) will be set. In addition, the
M
essage
E
rror
I
nfo
R
egister (MEIR) will be updated to reflect the number of
the object which suffered the message error, and the specific type of
message error encountered (Tx Buffer Underflow or Fragmentation
Error).
The MERIF interrupt flag is cleared by writing ‘1’ to the flag’s
position in CANINTFLG[3].
Tx Buffer Underflow
This condition occurs when the transmit engine is “starved” due to
the inability of the DMA to gain access to the bus. This interrupt
condition is predominantly for system debugging. It should never
occur during normal operation unless there is a serious flaw in the
system (e.g., a peripheral which asserts the WAIT signal for an
extended period).
Fragmentation Error
Fragmentation Error is an out–of–sequence Fragment count. For
each successive frame of a Fragmented message, the new
Fragment count must equal the previous count plus one. For
DeviceNet, the Fragment count field is 6 bits wide, for OSEK it is 4
bits wide, and for CANopen it is merely a single, toggling bit.
If a new start–of–message indicator is received for an object, while
the XA-C3 is already in the process of assembling a message for
that object, the pointers for that object will be automatically reset and
assembly will re–commence at the bottom of that object’s message
buffer. The previous, in–progress message will be overwritten, and
no interrupt or error flag of any kind will be generated.
Frame Error Interrupt
There are six conditions generated from within the CAN core, any of
which may cause the Frame Error Interrupt Flag (the FERIF bit in
CANINTFLG[4]) to be set:
Bus Error
Pre–Buffer Overflow
Arbitration Lost
Error Warning
Error Passive
Bus Off
Each condition has a corresponding status flag in the
F
rame
E
rror
St
atus
R
egister (FESTR), which will be set when that condition
occurs. Each condition also has a corresponding enable bit in the
F
rame
E
rror
En
able
R
egister (FEENR). If a particular condition’s
enable bit is set, then when hardware sets that condition’s status
flag, the Frame Error Interrupt Flag will also be set. The Frame
Error Interrupt Flag is cleared using a 2–step process:
1. The six individual Frame Error Status Flags in the FESTR
register must first be cleared. Details on clearing these flags will
be found in the following sections.
2. The FERIF bit can then be cleared by writing ‘1’ to the flag’s bit
position in CANINTFLG[4].
Bus Error
When a Bus Error occurs, the BERR status flag in FESTR[3] will be
set, generating a Frame Error interrupt, if enabled. The BERR status
flag is cleared by executing a read of the Error Code Capture
Register (ECCR).
The type and location of the error within the bit stream will be
encoded and stored in the Error Code Capture register for the
benefit of the User application. The ECCR register must be read by
the CPU in order to be reactivated for capturing the next error code,
as well as to clear the BERR status flag. Error codes in the ECCR
register are interpreted as shown in Table 25. A read of the ECCR
register should be executed before the Bus Error interrupt is
enabled.
Table 25. Error Codes for the Error Code Capture
Register (ECCR)
ECCR[7:6]
00
01
10
11
ECCR[5]
0
Interpretation
Bit Error
Form Error
Stuff Error
Other Error
Interpretation
Tx Error, error occurred during
transmission
Rx Error, error occurred during
reception
Interpretation
Start of Frame
ID28
…
ID21
ID20
…
ID18
SRR Bit
IDE Bit
ID17
…
ID13
ID12
…
ID5
ID4
…
ID0
RTR Bit
Reserved Bit 1
Reserved Bit 0
Data Length Code
Data Field
CRC Sequence
CRC Delimiter
Acknowledge slot
Acknowledge Delimiter
End Of Frame
Intermission (go buy popcorn)
Active Error Flag
Passive Error Flag
Tolerate DOM bits
Error Delimiter
Overload Flag
1
ECCR[4:0]
00011
00010
00110
00100
00101
00111
01111
01110
01100
01101
01001
01011
01010
01000
11000
11001
11011
11010
10010
10001
10110
10011
10111
11100
Pre–Buffer Overflow
The XA-C3 stores one complete frame (which can be up to 13
bytes) in a receive “pre–buffer” while the previous frame is being
processed. Even under extreme conditions, this should provide
ample time for the previous frame to be written to memory by DMA.
If for some reason the DMA is unable to gain access to the bus for a
long period of time, the pre–buffer could overflow. In this event, the
XA-C3 will stop accepting the new message. That is, once the five
pre–buffer bytes are full, subsequent incoming bits will be ignored.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PXB16050U | NPN microwave power transistor |
| PY08-02 | INDUSTRIERELAIS FASSUNG PCB |
| PY08-02186697 | SOCKET PCB |
| PY14 | INDUSTRIERELAIS CHASSIS MONTAGESOCKEL |
| PY14-02 | INDUSTRIERELAIS LEITERPL MONTAGESOCKEL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PXAC37KBA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| PXAC37KBBD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| PXAC37KFA | 功能描述:16位微控制器 - MCU OTP32K/1K 32 MHZ CAN EXT PLCC RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| PXAC37KFA/00,512 | 功能描述:IC XA MCU 16BIT 32K OTP 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:XA 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| PXAC37KFBD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。