參數(shù)資料
型號： PXAC37
廠商： NXP Semiconductors N.V.
英文描述： XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce
中文描述： 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce
文件頁數(shù)： 14/68頁
文件大?。?/td> 368K
代理商： PXAC37
Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
7
PIN DESCRIPTIONS
Table 4. Pin Descriptions
MNEMONIC
PIN NUMBERS
PLCC
1, 22
23, 44
TYPE
NAME AND FUNCTION
LQFP
16, 39
17, 38
V
SS
V
DD
I
I
Ground: 0V Reference.
Power Supply: This is the power supply voltage for normal, Idle and Power–Down op-
eration.
P0.0 – P0.7
43 – 36
37–30
I/O
Port 0: Port 0 is an 8–bit I/O Port with user –configurable pins. Port 0 latches have 1’s
written to them and are configured in the Quasi–Bidirectional mode during Reset. The
operation of Port 0 pins as inputs or outputs depends upon the Port configuration se-
lected. Each Port pin is configured independently. Refer to the sections on I/O Port
configuration and DC Electrical Characteristics for details.
NOTE:
2. When the External PROGRAM/DATA bus is used, Port 0 becomes the multiplexed
low DATA/Instruction Byte and Address lines 4 through 11.
Port 1: Port 1 is an 8–bit I/O Port with user –configurable pins. Port 1 latches have 1’s
written to them and are configured in the Quasi–Bidirectional mode during Reset. The
operation of Port 1 pins as inputs or outputs depends upon the Port configuration se-
lected. Each Port pin is configured independently. Refer to the sections on I/O Port
configuration and DC Electrical Characteristics for details.
WRH
/
: Address bit 0 of the External Address bus when the External DATA bus is config-
ured for 8–bit width. When the External DATA bus is used, this pin becomes the High
Byte Write Strobe (WRH).
A1: Address bit 1 of the External Address bus.
A2: Address bit 2 of the External Address bus.
A3: Address bit 3 of the External Address bus.
SPIRx: Receiver serial input of SPI.
SPITx: Transmitter serial output of SPI.
T2 ; SPICLK: Timer/counter 2 external clock input or Timer/counter 2 Clock–Out mode
output, or SPI Clock output.
NOTES:
3. SPICLK must be configured to idle in the logic ‘1’ state in order to use either the T2
or P1.6 output functions, even if the SPI Port is not in use!
4. The default state from Reset of the SPICLK polarity is “inverted” which yields an
SPICLK idle state of logic ‘1’.
5. If the SPI Clock polarity is changed by the user during SPI Port usage, it must be
restored to “inverted” polarity before using either the P1.6 or Timer/counter 2 output
functions.
P1.0 – P1.7
2 – 9
40 – 44
1 – 3
I/O
P1.0
2
40
O
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
3
4
5
6
7
8
41
42
43
44
1
2
O
O
O
I
O
I
P1.7
9
3
O
I/O
T2EX: Timer/counter 2 reload/capture/direction control.
Port 2: Port 2 is an 8–bit I/O port with user–configurable pins. Port 2 latches have 1’s
written to them and are configured in the Quasi–Bidirectional mode during Reset. The
operation of Port 2 pins as inputs or outputs depends upon the Port configuration se-
lected. Each Port pin is configured independently.
Refer to the sections on I/O port configuration and DC Electrical Characteristics for de-
tails.
NOTES:
6. When the External 16–bit PROGRAM/DATA bus is used, Port 2 is MUXed between
High (DATA/Instruction) Byte and Address lines 12 through 19.
Port 3: Port 3 is an 8–bit I/O Port with user–configurable pins.
NOTES:
7. Port 3 latches have 1’s written to them and are configured in the Quasi–Bidirectional
mode during Reset.
8. The operation of Port 3 pins as inputs or outputs depends upon the Port
configuration selected.
9. Each Port pin is configured independently.
Refer to the sections on I/O Port configuration and DC Electrical Characteristics for
details.
RxD0: Receiver serial input of UART 0.
TxD0: Transmitter serial output of UART 0.
INT0
/
: External interrupt 0 input.
INT1
/
: External interrupt 1 input.
P2.0 – P2.7
24 – 31
18 – 25
P3.0 – P3.7
11,
13 – 19
5,
7 –12
I/O
P3.0
P3.1
P3.2
P3.3
11
13
14
15
5
7
8
9
I
O
I
I
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