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| 型號(hào)： | PXAC37 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| 中文描述： | 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個(gè)SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce |
| 文件頁數(shù)： | 21/68頁 |
| 文件大小： | 368K |
| 代理商： | PXAC37 |
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Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
14
CP or
RL2/
BIT
T2CON.7
SYMBOL
TF2
FUNCTION
Timer 2 overflow flag. Set by hardware on Timer/Counter overflow. Must be cleared by software.
TF2 will not be set when RCLK0, RCLK1, TCLK0, TCLK1 or T2OE=1.
Timer 2 external flag is set when a capture or reload occurs due to a negative transition on T2EX (and
EXEN2 is set). This flag will cause a Timer 2 interrupt when this interrupt is enabled. EXF2 is cleared by
software.
Receive Clock Flag.
Transmit Clock Flag. RCLK0 and TCLK0 are used to select Timer 2 overflow rate as a clock source for
UART0 instead of Timer T1.
Timer 2 external enable bit allows a capture or reload to occur due to a negative transition on T2EX.
Start=1/Stop=0 control for Timer 2.
Timer or counter select.
0=Internal timer
1=External event counter (falling edge triggered)
CP or RL2/ Capture/Reload flag.
If CP/RL2 & EXEN2=1 captures will occur on negative transitions of T2EX.
If CP/RL2=0, EXEN2=1 auto reloads occur with either Timer 2 overflows or negative transitions at T2EX.
If RCLK or TCLK=1 the timer is set to auto reload on Timer 2 overflow, this bit has no effect.
T2CON.6
EXF2
T2CON.5
T2CON.4
RCLK0
TCLK0
T2CON.3
T2CON.2
T2CON.1
EXEN2
TR2
C2 or T2/
T2CON.0
SU001326
C2 or
T2/
TR2
EXEN2
TCLK0
RCLK0
EXF2
TF2
T2CON Address:418
Bit Addressable
Reset Value: 00H
LSB
MSB
Figure 8. Timer/Counter 2 Control (T2CON) Register
New Timer-Overflow Toggle Output
In the XA, the timer module now has two outputs, which toggle on
overflow from the individual timers. The same device pins that are
used for the T0 and T1 count inputs are also used for the new
overflow outputs. An SFR bit (TnOE in the TSTAT register – see
Figure 9 –– is associated with each counter and indicates whether
Port–SFR data or the overflow signal is output to the pin. These
outputs could be used in applications for generating variable duty
cycle PWM outputs (changing the auto–reload register values).
Also, variable frequency (
f
osc/8 to
f
osc/8,388,608) outputs could be
achieved by adjusting the prescaler along with the auto–reload
register values.
Timer T2
Timer 2 in the XA is a 16–bit Timer/Counter which can operate as
either a timer or as an event counter. This is selected by {C2 or T2
/
}
(T2CON[1]) (see Figure 8). Upon timer T2 overflow/underflow, the
TF2 flag is set, which may be used to generate an interrupt. It can
be operated in one of three operating modes: auto–reload (up or
down counting), capture, or as the baud rate generator (for the
UART via SFRs T2CON and T2MOD – see Figure 10.
These modes are shown in Table 7.
Capture Mode
In the capture mode there are two options which are selected by bit
EXEN2 (T2CON[3]). If EXEN2 = 0, then timer 2 is a 16–bit timer or
counter, which upon overflowing sets bit TF2 (T2CON[7]), the timer
2 overflow bit. This will cause an interrupt when the timer 2 interrupt
is enabled.
If EXEN2 = 1, then Timer 2 still does the above, but with the added
feature that a 1–to–0 transition at External input T2EX causes the
current value in the Timer 2 registers, TL2 and TH2, to be captured
into registers RCAP2L and RCAP2H, respectively. In addition, the
transition at T2EX causes bit EXF2 (T2CON[6]) to be set. This will
cause an interrupt in the same fashion as TF2 when the Timer 2
interrupt is enabled. The capture mode is illustrated in Figure 11.
Auto-Reload Mode (Up or Down Counter)
In the auto–reload mode, the timer registers are loaded with the
16–bit value in T2CAPH and T2CAPL when the count overflows.
T2CAPH and T2CAPL are initialized by software. If the EXEN2 bit
(T2CON[3]) is set, the timer registers will also be reloaded and the
EXF2 flag T2CON[6] set when a 1–to–0 transition occurs at input
T2EX. The auto–reload mode is shown in Figure 12.
In this mode, Timer 2 can be configured to count up or down. This is
done by setting or clearing the DCEN (Down Counter Enable) bit
T2MOD[0] (see Table 7). The T2EX pin then controls the count
direction. When T2EX is high, the count is in the up direction, when
T2EX is low, the count is in the down direction.
Figure 12 shows Timer 2, which will count up automatically, since
DCEN = 0. In this mode there are two options selected by bit
EXEN2 in the T2CON register. If EXEN2 bit = 0, then Timer 2 counts
up to FFFFh and sets the TF2 (Overflow Flag) bit T2CON[7] upon
overflow. This causes the Timer 2 registers to be reloaded with the
16–bit value in T2CAPL and T2CAPH, whose values are preset by
software. If EXEN2 bit T2CON[3] = 1, a 16–bit reload can be
triggered either by an overflow or by a 1–to–0 transition at input
T2EX. This transition also sets the EXF2 bit. If enabled, either TF2
bit or EXF2 bit can generate the Timer 2 interrupt.
In Figure 13 where the DCEN bit = 1; this enables the Timer 2 to
count up or down. In this mode, the logic level of T2EX pin controls
the direction of count. When a logic ‘1’ is applied at pin T2EX, the
Timer 2 will count up. The Timer 2 will overflow at FFFFh and set the
TF2 bit flag, which can then generate an interrupt if enabled. This
timer overflow also causes the 16–bit value in T2CAPL and
T2CAPH to be reloaded into timer registers TL2 and TH2,
respectively.
A logic ‘0’ at pin T2EX causes Timer 2 to count down. When
counting down, the timer value is compared to the 16–bit value
contained in T2CAPH and T2CAPL. When the value is equal, the
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