參數(shù)資料
型號(hào)： PT7A6632J
廠商： Pericom Semiconductor Corp.
英文描述： PT7A6632 32-Channel HDLC Controller
中文描述： PT7A6632 32通道HDLC控制器
文件頁數(shù)： 37/61頁
文件大?。?/td> 379K
代理商： PT7A6632J
Data Sheet
PT7A6632 32-Channel HDLC Controller
PT019(05/02)
Ver:2
37
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FILL/MASK Byte (Rate Definition)
The PT7A6632 FILL/MASK byte is used as a masking pattern
on the HDLC-formatted (including FLAG, header, data, CRC,
and ABORT code) or non-HDLC-formatted data in order to
adapt subrates that are multiples of 8kb/s to the 64kb/s rate.
The 8-bit sequence is applied to data on a bit by bit basis to
remove time-fill (FILL/MASK bit = 0) bits. See an example in
Figure 13 in Section “Receive Bit-Level Processor” and Table
9.
For bit-oriented signaling mode, the FILL/MASK should be
set as 1111 1111, otherwise the PT7A6632 will not override
any other FILL/MASK pattern.
Flexible Hyperchannel Configuring Byte (Optional)
The byte follows the FILL/MASK byte if any. It is used to
configure flexible hyperchannel. Bits 0 - 4 specify number of
a channel to be grouped into or removed from a hyperchannel.
Bits 6 and 7 is for hyperchannel enable and add/delete respec-
tively. See Table 10 for details.
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r
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Data Length is used to specify flexible hyperchannel. When
Data Length = 0, 1 or 2, only non-hyperchannel process. When
Data Length > 2, there is hyperchannel process, while the Data
Length indicates how many additional channels to be added
to the hyperchannel. See Section “Flexible Hyperchannel” in
Transmit Command Buffer.
Minimum Buffer Size
The size of receive data buffer must ensure normal buffer main-
tenance and buffer transition without losing data.
Table 15
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