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參數(shù)資料
| 型號： | PT7A6632J |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | PT7A6632 32-Channel HDLC Controller |
| 中文描述： | PT7A6632 32通道HDLC控制器 |
| 文件頁數(shù)： | 16/61頁 |
| 文件大?。?/td> | 379K |
| 代理商： | PT7A6632J |
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Data Sheet
PT7A6632 32-Channel HDLC Controller
PT019(05/02)
Ver:2
16
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A B C D E F G H
MSB
LSB
Received Data
1 0 1 1 1 0 0 0
FILL/MASK
A 1 B C D 1 1 1 E 1 F G H 1 1 1
T1/CEPT PCM-30 Serial Input
TS m in Frame n+1 TS m in Frame n
Assembled Data Byte
Figure 13. 32kb/s Subrate Operation - Single Receive Channel
Figure 14. Receive Frame Synchronization Timing - T1 Mode, SIS = 1
~
~
~
~
Proving Period 1
(
≤
one full
multiframe)
Proving Period 2
(one full
multiframe)
Proving Period 3
(one full
multiframe)
(One full
multiframe)
From this point, fully
multiframe synchronized
until RRED goes high
Channel 1, first frame of the next
multiframe
Channel 24, last
frame of a
multiframe
Bit 7 Bit 8 Bit F Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
RRED
RSYNC
RCLK
RSER
RRED
RSYNC
~
~
~
~
HDLC Mode
In HDLC mode, the Receive Processor detects flags, abort,
delete zero-bit, check the Frame Check Sequences (FCS), and
filters the time-fill bits by applying FILL/MASK byte to the
received data.
Reset the device will make all channels in HDLC mode.
Non-HDLC Data Mode
In this mode, received data are directly written into external
memory without deformating.
Non-HDLC Signaling Mode
In non-HDLC signaling mode, PT7A6632 detects the
multiframe alignment sequence. If the alignment sequence is
valid, the received data will be sent to the external memory; if
not, the data will not be sent to external memory until a valid
alignment sequence is detected. The loss of the multiframe
alignment will be reported to external memory. Any channel(s)
can be specified to receive bit-oriented signaling. This feature
is very useful in central office switching applications.
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